Lines Matching full:arm
1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
10 // This file defines an instruction selector for the ARM target.
14 #define DEBUG_TYPE "arm-isel"
15 #include "ARM.h"
52 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
77 return "ARM Instruction Selection";
201 /// ARM.
239 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
242 /// SelectCMOVOp - Select CMOV instructions for ARM.
417 /// least on current ARM implementations) which should be avoidded.
443 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
1100 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1101 (RHSR && RHSR->getReg() == ARM::SP))
1165 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1166 (RHSR && RHSR->getReg() == ARM::SP)) {
1226 (LHSR && LHSR->getReg() == ARM::SP)) {
1469 Opcode = ARM::LDR_PRE_IMM;
1473 Opcode = ARM::LDR_POST_IMM;
1477 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1484 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1485 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1490 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1496 Opcode = ARM::LDRB_PRE_IMM;
1500 Opcode = ARM::LDRB_POST_IMM;
1503 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1509 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1544 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1548 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1550 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1555 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1557 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1581 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
1582 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
1583 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
1592 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1593 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1594 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1602 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1603 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1604 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1612 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1613 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1614 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1624 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1625 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1626 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1627 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1628 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1638 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1639 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1640 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1641 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1642 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1652 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1653 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1654 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1655 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1656 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1689 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1690 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1691 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1692 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1693 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1694 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1695 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1696 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1698 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1699 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1700 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1701 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1702 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1703 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1704 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1705 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1706 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1707 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1709 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1710 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1711 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1712 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1713 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1714 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1716 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1717 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1718 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1719 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1720 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1721 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1723 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1724 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1725 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1800 if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) ||
1850 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1851 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1852 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1950 if ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) ||
2114 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
2115 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
2116 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2198 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2199 unsigned SubIdx = ARM::dsub_0;
2248 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2249 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2274 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2281 // ARM models shift instructions as MOVsi with shifter operand.
2288 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops, 5);
2334 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2335 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2336 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2337 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2359 return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2365 return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2380 Opc = ARM::t2MOVCCi;
2382 Opc = ARM::t2MOVCCi16;
2385 Opc = ARM::t2MVNCCi;
2388 Opc = ARM::t2MOVCCi32imm;
2412 Opc = ARM::MOVCCi;
2414 Opc = ARM::MOVCCi16;
2417 Opc = ARM::MVNCCi;
2421 Opc = ARM::MOVCCi32imm;
2509 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2510 : ARM::MOVCCr;
2513 Opc = ARM::VMOVScc;
2516 Opc = ARM::VMOVDcc;
2530 /// ARM instruction selection detects the latter and matches it to
2531 /// ARM::ABS or ARM::t2ABS machine node.
2554 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2575 if (Opc == ARM::ATOMCMPXCHG6432) {
2640 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2650 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2668 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2671 ARM::t2ADDri : ARM::ADDri);
2702 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2705 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2718 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2721 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2740 ? ARM::t2MOVTi16
2741 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2768 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2777 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
2783 ARM::UMULL : ARM::UMULLv5,
2793 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
2799 ARM::SMULL : ARM::SMULLv5,
2808 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
2815 ARM::UMLAL : ARM::UMLALv5,
2824 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
2831 ARM::SMLAL : ARM::SMLALv5,
2860 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2892 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2893 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2896 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2897 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2898 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2900 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2912 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2913 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2916 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2917 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2918 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2920 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2932 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2933 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2935 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2936 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2937 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2939 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2963 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2964 ARM::VLD2DUPd32 };
2969 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
2970 ARM::VLD3DUPd16Pseudo,
2971 ARM::VLD3DUPd32Pseudo };
2976 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
2977 ARM::VLD4DUPd16Pseudo,
2978 ARM::VLD4DUPd32Pseudo };
2983 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
2984 ARM::VLD2DUPd16wb_fixed,
2985 ARM::VLD2DUPd32wb_fixed };
2990 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
2991 ARM::VLD3DUPd16Pseudo_UPD,
2992 ARM::VLD3DUPd32Pseudo_UPD };
2997 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
2998 ARM::VLD4DUPd16Pseudo_UPD,
2999 ARM::VLD4DUPd32Pseudo_UPD };
3004 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
3005 ARM::VLD1d16wb_fixed,
3006 ARM::VLD1d32wb_fixed,
3007 ARM::VLD1d64wb_fixed };
3008 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
3009 ARM::VLD1q16wb_fixed,
3010 ARM::VLD1q32wb_fixed,
3011 ARM::VLD1q64wb_fixed };
3016 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
3017 ARM::VLD2d16wb_fixed,
3018 ARM::VLD2d32wb_fixed,
3019 ARM::VLD1q64wb_fixed};
3020 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
3021 ARM::VLD2q16PseudoWB_fixed,
3022 ARM::VLD2q32PseudoWB_fixed };
3027 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
3028 ARM::VLD3d16Pseudo_UPD,
3029 ARM::VLD3d32Pseudo_UPD,
3030 ARM::VLD1q64wb_fixed};
3031 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3032 ARM::VLD3q16Pseudo_UPD,
3033 ARM::VLD3q32Pseudo_UPD };
3034 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
3035 ARM::VLD3q16oddPseudo_UPD,
3036 ARM::VLD3q32oddPseudo_UPD };
3041 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
3042 ARM
3043 ARM::VLD4d32Pseudo_UPD,
3044 ARM::VLD1q64wb_fixed};
3045 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3046 ARM::VLD4q16Pseudo_UPD,
3047 ARM::VLD4q32Pseudo_UPD };
3048 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
3049 ARM::VLD4q16oddPseudo_UPD,
3050 ARM::VLD4q32oddPseudo_UPD };
3055 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
3056 ARM::VLD2LNd16Pseudo_UPD,
3057 ARM::VLD2LNd32Pseudo_UPD };
3058 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
3059 ARM::VLD2LNq32Pseudo_UPD };
3064 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
3065 ARM::VLD3LNd16Pseudo_UPD,
3066 ARM::VLD3LNd32Pseudo_UPD };
3067 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
3068 ARM::VLD3LNq32Pseudo_UPD };
3073 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
3074 ARM::VLD4LNd16Pseudo_UPD,
3075 ARM::VLD4LNd32Pseudo_UPD };
3076 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
3077 ARM::VLD4LNq32Pseudo_UPD };
3082 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
3083 ARM::VST1d16wb_fixed,
3084 ARM::VST1d32wb_fixed,
3085 ARM::VST1d64wb_fixed };
3086 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
3087 ARM::VST1q16wb_fixed,
3088 ARM::VST1q32wb_fixed,
3089 ARM::VST1q64wb_fixed };
3094 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
3095 ARM::VST2d16wb_fixed,
3096 ARM::VST2d32wb_fixed,
3097 ARM::VST1q64wb_fixed};
3098 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
3099 ARM::VST2q16PseudoWB_fixed,
3100 ARM::VST2q32PseudoWB_fixed };
3105 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
3106 ARM::VST3d16Pseudo_UPD,
3107 ARM::VST3d32Pseudo_UPD,
3108 ARM::VST1d64TPseudoWB_fixed};
3109 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3110 ARM::VST3q16Pseudo_UPD,
3111 ARM::VST3q32Pseudo_UPD };
3112 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
3113 ARM::VST3q16oddPseudo_UPD,
3114 ARM::VST3q32oddPseudo_UPD };
3119 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
3120 ARM::VST4d16Pseudo_UPD,
3121 ARM::VST4d32Pseudo_UPD,
3122 ARM::VST1d64QPseudoWB_fixed};
3123 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3124 ARM::VST4q16Pseudo_UPD,
3125 ARM::VST4q32Pseudo_UPD };
3126 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
3127 ARM::VST4q16oddPseudo_UPD,
3128 ARM::VST4q32oddPseudo_UPD };
3133 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
3134 ARM::VST2LNd16Pseudo_UPD,
3135 ARM::VST2LNd32Pseudo_UPD };
3136 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
3137 ARM::VST2LNq32Pseudo_UPD };
3142 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
3143 ARM::VST3LNd16Pseudo_UPD,
3144 ARM::VST3LNd32Pseudo_UPD };
3145 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
3146 ARM::VST3LNq32Pseudo_UPD };
3151 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
3152 ARM::VST4LNd16Pseudo_UPD,
3153 ARM::VST4LNd32Pseudo_UPD };
3154 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
3155 ARM::VST4LNq32Pseudo_UPD };
3172 unsigned NewOpc = isThumb ? ARM::t2LDREXD :ARM::LDREXD;
3202 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
3214 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
3250 unsigned NewOpc = isThumb ? ARM::t2STREXD : ARM::STREXD;
3262 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3263 ARM::VLD1d32, ARM::VLD1d64 };
3264 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3265 ARM::VLD1q32, ARM::VLD1q64};
3270 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3271 ARM::VLD2d32, ARM::VLD1q64 };
3272 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3273 ARM::VLD2q32Pseudo };
3278 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3279 ARM::VLD3d16Pseudo,
3280 ARM::VLD3d32Pseudo,
3281 ARM::VLD1d64TPseudo };
3282 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3283 ARM::VLD3q16Pseudo_UPD,
3284 ARM::VLD3q32Pseudo_UPD };
3285 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3286 ARM::VLD3q16oddPseudo,
3287 ARM::VLD3q32oddPseudo };
3292 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3293 ARM::VLD4d16Pseudo,
3294 ARM::VLD4d32Pseudo,
3295 ARM::VLD1d64QPseudo };
3296 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3297 ARM::VLD4q16Pseudo_UPD,
3298 ARM::VLD4q32Pseudo_UPD };
3299 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3300 ARM::VLD4q16oddPseudo,
3301 ARM::VLD4q32oddPseudo };
3306 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3307 ARM::VLD2LNd16Pseudo,
3308 ARM::VLD2LNd32Pseudo };
3309 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3310 ARM::VLD2LNq32Pseudo };
3315 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3316 ARM::VLD3LNd16Pseudo,
3317 ARM::VLD3LNd32Pseudo };
3318 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3319 ARM::VLD3LNq32Pseudo };
3324 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3325 ARM::VLD4LNd16Pseudo,
3326 ARM::VLD4LNd32Pseudo };
3327 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3328 ARM::VLD4LNq32Pseudo };
3333 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3334 ARM::VST1d32, ARM::VST1d64 };
3335 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3336 ARM::VST1q32, ARM::VST1q64 };
3341 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3342 ARM::VST2d32, ARM::VST1q64 };
3343 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3344 ARM::VST2q32Pseudo };
3349 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3350 ARM::VST3d16Pseudo,
3351 ARM::VST3d32Pseudo,
3352 ARM::VST1d64TPseudo };
3353 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3354 ARM::VST3q16Pseudo_UPD,
3355 ARM::VST3q32Pseudo_UPD };
3356 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3357 ARM::VST3q16oddPseudo,
3358 ARM::VST3q32oddPseudo };
3363 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3364 ARM::VST4d16Pseudo,
3365 ARM::VST4d32Pseudo,
3366 ARM::VST1d64QPseudo };
3367 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3368 ARM::VST4q16Pseudo_UPD,
3369 ARM::VST4q32Pseudo_UPD };
3370 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3371 ARM::VST4q16oddPseudo,
3372 ARM::VST4q32oddPseudo };
3377 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3378 ARM::VST2LNd16Pseudo,
3379 ARM::VST2LNd32Pseudo };
3380 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3381 ARM::VST2LNq32Pseudo };
3386 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3387 ARM::VST3LNd16Pseudo,
3388 ARM::VST3LNd32Pseudo };
3389 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3390 ARM::VST3LNq32Pseudo };
3395 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3396 ARM::VST4LNd16Pseudo,
3397 ARM::VST4LNd32Pseudo };
3398 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3399 ARM::VST4LNq32Pseudo };
3413 return SelectVTBL(N, false, 2, ARM::VTBL2);
3415 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3417 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3420 return SelectVTBL(N, true, 2, ARM::VTBX2);
3422 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3424 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3438 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
3454 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
3461 return SelectAtomic64(N, ARM::ATOMOR6432);
3463 return SelectAtomic64(N, ARM::ATOMXOR6432);
3465 return SelectAtomic64(N, ARM::ATOMADD6432);
3467 return SelectAtomic64(N, ARM::ATOMSUB6432);
3469 return SelectAtomic64(N, ARM::ATOMNAND6432);
3471 return SelectAtomic64(N, ARM::ATOMAND6432);
3473 return SelectAtomic64(N, ARM::ATOMSWAP6432);
3475 return SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
3478 return SelectAtomic64(N, ARM::ATOMMIN6432);
3480 return SelectAtomic64(N, ARM::ATOMUMIN6432);
3482 return SelectAtomic64(N, ARM::ATOMMAX6432);
3484 return SelectAtomic64(N, ARM::ATOMUMAX6432);
3497 // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
3550 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
3567 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3576 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
3578 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
3604 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3617 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
3645 // Require the address to be in a register. That is safe for all ARM
3653 /// ARM-specific DAG, ready for instruction scheduling.
