Lines Matching defs:CC
76 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
79 : CCState(CC, isVarArg, MF, TM, locs, C) {
1178 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1179 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1180 switch (CC) {
1195 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1196 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1199 switch (CC) {
1232 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1235 switch (CC) {
3038 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3045 switch (CC) {
3050 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3057 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3064 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3071 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3079 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3184 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3192 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3197 FPCCToARMCC(CC, CondCode, CondCode2);
3286 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3300 if (CC == ISD::SETOEQ)
3301 CC = ISD::SETEQ;
3302 else if (CC == ISD::SETUNE)
3303 CC = ISD::SETNE;
3312 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3324 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3336 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3344 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3353 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3354 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3361 FPCCToARMCC(CC, CondCode, CondCode2);
4013 SDValue CC = Op.getOperand(2);
4015 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6311 bool IsMinMax, ARMCC::CondCodes CC) const {
6430 .addMBB(exitMBB).addImm(CC).addReg(ARM::CPSR);
7655 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7772 // Detects these expressions where cc is an i1 value:
7774 // (select cc 0, y) [AllOnes=0]
7775 // (select cc y, 0) [AllOnes=0]
7776 // (zext cc) [AllOnes=0]
7777 // (sext cc) [AllOnes=0/1]
7778 // (select cc -1, y) [AllOnes=1]
7779 // (select cc y, -1) [AllOnes=1]
7781 // Invert is set when N is the null/all ones constant when CC is false.
7784 SDValue &CC, bool &Invert,
7790 CC = N->getOperand(0);
7806 // (zext cc) can never be the all ones value.
7812 CC = N->getOperand(0);
7813 if (CC.getValueType() != MVT::i1)
7832 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7833 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7834 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
7835 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7836 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
7843 // (add (zext cc), x) -> (select cc (add x, 1), x)
7844 // (add (sext cc), x) -> (select cc (add x, -1), x)
7867 // Slct is now know to be the desired identity constant when CC is true.
7871 // Unless SwapSelectOps says CC should be false.
8151 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8183 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8346 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8389 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8563 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
9706 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9711 IsReversed = false; // x CC y ? x : y
9713 IsReversed = true ; // x CC y ? y : x
9719 switch (CC) {
9730 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9736 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
9752 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
9758 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
9786 ARMCC::CondCodes CC =
9807 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
9810 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
10572 if (StringRef("{cc}").equals_lower(Constraint))
