Lines Matching defs:Opcode
958 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
959 switch (Opcode) {
3443 default: llvm_unreachable("Invalid opcode!");
3473 default: llvm_unreachable("Invalid opcode!");
3497 default: llvm_unreachable("Invalid opcode!");
3950 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
5027 default: llvm_unreachable("Unknown shuffle opcode!");
5480 unsigned Opcode = N->getOpcode();
5481 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5491 unsigned Opcode = N->getOpcode();
5492 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
7363 default: llvm_unreachable("unexpected opcode!");
7501 // true/false values to select between, and a branch opcode to use.
7611 // true/false values to select between, and a branch opcode to use.
7711 "converted opcode should be the same except for cc_out");
8071 // Figure out the right opcode.
8209 unsigned Opcode = N0.getOpcode();
8210 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8211 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8212 Opcode = N1.getOpcode();
8213 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8214 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8223 return DAG.getNode(Opcode, DL, VT,
9039 // Find the new opcode for the updating load/store.
9080 default: llvm_unreachable("unexpected opcode for Neon base update");
9419 /// operand of a vector shift right operation. For a shift opcode, the value
9527 // Opcode already set above.
9626 default: llvm_unreachable("unexpected shift opcode");
9670 default: llvm_unreachable("unexpected opcode");
9708 unsigned Opcode = 0;
9740 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
9762 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
9766 if (!Opcode)
9768 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
10747 unsigned Opcode = Op->getOpcode();
10748 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10749 "Invalid opcode for Div/Rem lowering");
10750 bool isSigned = (Opcode == ISD::SDIVREM);
