Lines Matching refs:V1
3829 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
3855 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
3881 /// input = [v0 v1 ] (vi: 32-bit elements)
5070 SDValue V1 = Op.getOperand(0);
5080 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5084 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5107 SDValue V1 = Op.getOperand(0);
5128 // Test if V1 is a SCALAR_TO_VECTOR.
5129 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5130 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5132 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5135 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5136 !isa<ConstantSDNode>(V1.getOperand(0))) {
5138 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5139 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5144 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5146 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5154 std::swap(V1, V2);
5155 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5160 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5162 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5164 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5168 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5180 V1, V2).getValue(WhichResult);
5183 V1, V2).getValue(WhichResult);
5186 V1, V2).getValue(WhichResult);
5190 V1, V1
5193 V1, V1).getValue(WhichResult);
5196 V1, V1).getValue(WhichResult);
5218 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5227 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5235 ShuffleMask[i] < (int)NumElts ? V1 : V2,
7613 // V1 = ABS V0
7618 // SinkBB: V1 = PHI(V2, V3)
8971 // shuffle(concat(v1, undef), concat(v2, undef)) ->
8972 // shuffle(concat(v1, v2), undef)
