Lines Matching full:itin
581 class VLDQPseudo<InstrItinClass itin>
582 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
583 class VLDQWBPseudo<InstrItinClass itin>
585 (ins addrmode6:$addr, am6offset:$offset), itin,
587 class VLDQWBfixedPseudo<InstrItinClass itin>
589 (ins addrmode6:$addr), itin,
591 class VLDQWBregisterPseudo<InstrItinClass itin>
593 (ins addrmode6:$addr, rGPR:$offset), itin,
596 class VLDQQPseudo<InstrItinClass itin>
597 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
598 class VLDQQWBPseudo<InstrItinClass itin>
600 (ins addrmode6:$addr, am6offset:$offset), itin,
602 class VLDQQWBfixedPseudo<InstrItinClass itin>
604 (ins addrmode6:$addr), itin,
606 class VLDQQWBregisterPseudo<InstrItinClass itin>
608 (ins addrmode6:$addr, rGPR:$offset), itin,
612 class VLDQQQQPseudo<InstrItinClass itin>
613 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
615 class VLDQQQQWBPseudo<InstrItinClass itin>
617 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
775 InstrItinClass itin>
777 (ins addrmode6:$Rn), itin,
798 RegisterOperand VdTy, InstrItinClass itin> {
800 (ins addrmode6:$Rn), itin,
808 (ins addrmode6:$Rn, rGPR:$Rm), itin,
960 class VLDQLNPseudo<InstrItinClass itin>
963 itin, "$src = $dst">;
964 class VLDQLNWBPseudo<InstrItinClass itin>
967 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
968 class VLDQQLNPseudo<InstrItinClass itin>
971 itin, "$src = $dst">;
972 class VLDQQLNWBPseudo<InstrItinClass itin>
975 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
976 class VLDQQQQLNPseudo<InstrItinClass itin>
979 itin, "$src = $dst">;
980 class VLDQQQQLNWBPseudo<InstrItinClass itin>
983 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1525 class VSTQPseudo<InstrItinClass itin>
1526 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1527 class VSTQWBPseudo<InstrItinClass itin>
1529 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1531 class VSTQWBfixedPseudo<InstrItinClass itin>
1533 (ins addrmode6:$addr, QPR:$src), itin,
1535 class VSTQWBregisterPseudo<InstrItinClass itin>
1537 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1539 class VSTQQPseudo<InstrItinClass itin>
1540 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1541 class VSTQQWBPseudo<InstrItinClass itin>
1543 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1545 class VSTQQWBfixedPseudo<InstrItinClass itin>
1547 (ins addrmode6:$addr, QQPR:$src), itin,
1549 class VSTQQWBregisterPseudo<InstrItinClass itin>
1551 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1554 class VSTQQQQPseudo<InstrItinClass itin>
1555 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1556 class VSTQQQQWBPseudo<InstrItinClass itin>
1558 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1722 InstrItinClass itin>
1724 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1924 class VSTQLNPseudo<InstrItinClass itin>
1926 itin, "">;
1927 class VSTQLNWBPseudo<InstrItinClass itin>
1930 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1931 class VSTQQLNPseudo<InstrItinClass itin>
1933 itin, "">;
1934 class VSTQQLNWBPseudo<InstrItinClass itin>
1937 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1938 class VSTQQQQLNPseudo<InstrItinClass itin>
1940 itin, "">;
1941 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1944 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2341 InstrItinClass itin, string OpcodeStr, string Dt,
2344 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2348 InstrItinClass itin, string OpcodeStr, string Dt,
2351 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2356 InstrItinClass itin, string OpcodeStr, string Dt,
2359 itin, OpcodeStr, Dt, ResTy, OpTy,
2363 InstrItinClass itin, string OpcodeStr, string Dt,
2366 itin, OpcodeStr, Dt, ResTy, OpTy,
2372 InstrItinClass itin, string OpcodeStr, string Dt,
2375 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2381 InstrItinClass itin, string OpcodeStr, string Dt,
2384 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2390 InstrItinClass itin, string OpcodeStr, string Dt,
2393 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2399 InstrItinClass itin, string OpcodeStr, string Dt,
2402 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2412 InstrItinClass itin, string OpcodeStr, string Dt>
2414 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2419 InstrItinClass itin, string OpcodeStr, string Dt,
2422 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2431 InstrItinClass itin, string OpcodeStr,
2435 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2444 InstrItinClass itin, string OpcodeStr, string Dt,
2448 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2470 InstrItinClass itin, string OpcodeStr, string Dt,
2473 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2481 InstrItinClass itin, string OpcodeStr,
2484 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2492 InstrItinClass itin, string OpcodeStr, string Dt,
2496 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2521 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2524 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2533 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2537 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin, OpcodeStr, Dt,
2541 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2545 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2553 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2557 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2564 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2567 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2575 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2578 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2587 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2591 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2595 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2600 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2607 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2612 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2620 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2623 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2632 InstrItinClass itin, string OpcodeStr, string Dt,
2635 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2640 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2646 NVMulSLFrm, itin,
2653 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2659 NVMulSLFrm, itin,
2668 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2671 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2675 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2681 NVMulSLFrm, itin,
2688 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2695 NVMulSLFrm, itin,
2705 InstrItinClass itin, string OpcodeStr, string Dt,
2708 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2713 InstrItinClass itin, string OpcodeStr, string Dt,
2716 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2724 InstrItinClass itin, string OpcodeStr, string Dt,
2727 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2732 InstrItinClass itin, string OpcodeStr, string Dt,
2735 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2742 InstrItinClass itin, string OpcodeStr, string Dt,
2745 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2751 InstrItinClass itin, string OpcodeStr, string Dt,
2755 NVMulSLFrm, itin,
2763 InstrItinClass itin, string OpcodeStr, string Dt,
2767 NVMulSLFrm, itin,
2777 InstrItinClass itin, string OpcodeStr, string Dt,
2781 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2790 InstrItinClass itin, string OpcodeStr, string Dt,
2793 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2797 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2803 NVMulSLFrm, itin,
2811 InstrItinClass itin, string OpcodeStr, string Dt,
2816 NVMulSLFrm, itin,
2837 InstrItinClass itin, string OpcodeStr, string Dt,
2840 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2846 InstrItinClass itin, string OpcodeStr, string Dt,
2850 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2855 InstrItinClass itin, string OpcodeStr, string Dt,
2859 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2866 InstrItinClass itin, string OpcodeStr, string Dt,
2870 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2879 InstrItinClass itin, string OpcodeStr, string Dt,
2883 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2892 InstrItinClass itin, string OpcodeStr, string Dt,
2895 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2900 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2905 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2911 InstrItinClass itin, string OpcodeStr, string Dt,
2915 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2975 Format f, InstrItinClass itin, Operand ImmTy,
2978 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2982 Format f, InstrItinClass itin, Operand ImmTy,
2985 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3002 InstrItinClass itin, string OpcodeStr, string Dt,
3005 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3154 InstrItinClass itin, string OpcodeStr, string Dt,
3157 itin, OpcodeStr, !strconcat(Dt, "16"),
3160 itin, OpcodeStr, !strconcat(Dt, "32"),
3163 itin, OpcodeStr, !strconcat(Dt, "64"),
3171 InstrItinClass itin, string OpcodeStr, string Dt,
3174 itin, OpcodeStr, !strconcat(Dt, "16"),
3177 itin, OpcodeStr, !strconcat(Dt, "32"),
3180 itin, OpcodeStr, !strconcat(Dt, "64"),
3409 InstrItinClass itin, string OpcodeStr, string Dt,
3411 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3413 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3448 InstrItinClass itin, string OpcodeStr, string Dt,
3450 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3452 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3470 InstrItinClass itin, string OpcodeStr, string Dt,
3472 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3475 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3478 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3640 InstrItinClass itin, string OpcodeStr, string Dt,
3642 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3645 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3648 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3704 InstrItinClass itin, string OpcodeStr, string Dt,
3707 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3711 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3715 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3719 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3724 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3728 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3732 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3736 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3741 InstrItinClass itin, string OpcodeStr, string Dt,
3744 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3748 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3752 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3756 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3761 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3765 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3769 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3773 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3914 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3916 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3921 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3926 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
