Lines Matching full:arm
1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
147 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
150 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
153 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
156 return STI.getFeatureBits() & ARM::HasV4TOps;
159 return STI.getFeatureBits() & ARM::HasV6Ops;
162 return STI.getFeatureBits() & ARM::HasV7Ops;
165 return STI.getFeatureBits() & ARM::HasV8Ops;
168 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
172 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
176 return STI.getFeatureBits() & ARM::FeatureMClass;
261 // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
285 /// ARMOperand - Instances of this class represent a parsed ARM machine
378 /// Combined record for all forms of ARM address expressions.
627 if(Memory.BaseRegNum != ARM::PC) return false;
976 if (Memory.BaseRegNum != ARM::PC)
1115 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1148 if (Memory.BaseRegNum == ARM::PC) return false;
1166 if (Memory.BaseRegNum == ARM::PC) return false;
1227 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1243 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1270 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1498 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2321 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2323 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2614 .Case("r13", ARM::SP)
2615 .Case("r14", ARM::LR)
2616 .Case("r15", ARM::PC)
2617 .Case("ip", ARM::R12)
2619 .Case("a1", ARM::R0)
2620 .Case("a2", ARM::R1)
2621 .Case("a3", ARM::R2)
2622 .Case("a4", ARM::R3)
2623 .Case("v1", ARM::R4)
2624 .Case("v2", ARM::R5)
2625 .Case("v3", ARM::R6)
2626 .Case("v4", ARM::R7)
2627 .Case("v5", ARM::R8)
2628 .Case("v6", ARM::R9)
2629 .Case("v7", ARM::R10)
2630 .Case("v8", ARM::R11)
2631 .Case("sb", ARM::R9)
2632 .Case("sl", ARM::R10)
2633 .Case("fp", ARM::R11)
2958 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2962 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2963 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2964 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2965 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2966 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2967 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2968 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2969 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2977 case ARM::Q0: return ARM::D0;
2978 case ARM::Q1: return ARM::D2;
2979 case ARM::Q2: return ARM::D4;
2980 case ARM::Q3: return ARM::D6;
2981 case ARM::Q4: return ARM::D8;
2982 case ARM::Q5: return ARM::D10;
2983 case ARM::Q6: return ARM::D12;
2984 case ARM::Q7: return ARM::D14;
2985 case ARM::Q8: return ARM::D16;
2986 case ARM::Q9: return ARM::D18;
2987 case ARM::Q10: return ARM::D20;
2988 case ARM::Q11: return ARM::D22;
2989 case ARM::Q12: return ARM::D24;
2990 case ARM::Q13: return ARM::D26;
2991 case ARM::Q14: return ARM::D28;
2992 case ARM::Q15: return ARM::D30;
3017 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3024 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3025 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3026 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3027 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3028 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3029 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3049 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3079 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3088 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3099 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3118 // The ARM system instruction variants for LDM/STM have a '^' token here.
3192 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3212 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3219 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3220 ARM::DPairRegClassID]);
3224 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3225 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3257 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3287 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3294 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3333 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3398 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3399 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3400 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3411 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3412 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3413 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3590 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
4105 /// Parse an ARM memory expression, return false if successful else return true
4430 /// Parse a arm instruction operand. For now this parses the operand regardless
4549 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4769 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4795 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4850 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4871 (ARMMCRegisterClasses[ARM::DPRRegClassID]
4873 ARMMCRegisterClasses[ARM::QPRRegClassID]
4881 if (hasV8Ops() && Inst.getOpcode() == ARM::SETEND) {
4905 /// Parse an arm instruction mnemonic followed by its operands.
4918 // First check for the ARM-specific .req directive.
5003 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5034 // For for ARM mode generate an error if the .n qualifier is used.
5038 "arm mode");
5042 // and matcher expect. In ARM mode the .w qualifier has no effect,
5083 // table driven matcher doesn't fit well with the ARM instruction set.
5099 // ARM mode 'blx' need special handling, as the register operand version
5124 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5140 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5141 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5157 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5159 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5223 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5224 Inst.getOpcode() != ARM::BKPT) {
5250 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5251 Inst.getOpcode() != ARM::t2B)
5255 case ARM::LDRD:
5256 case ARM::LDRD_PRE:
5257 case ARM::LDRD_POST: {
5266 case ARM::STRD: {
5275 case ARM::STRD_PRE:
5276 case ARM::STRD_POST: {
5285 case ARM::SBFX:
5286 case ARM::UBFX: {
5295 case ARM::tLDMIA: {
5324 case ARM::t2LDMIA_UPD: {
5331 case ARM::tMUL: {
5353 case ARM::tPOP: {
5355 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5361 case ARM::tPUSH: {
5363 if (checkLowRegisterList(Inst, 2, 0, ARM
5369 case ARM::tSTMIA_UPD: {
5376 case ARM::tADDrSP: {
5399 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5400 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5401 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5402 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5403 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5404 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5405 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5406 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5407 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5410 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5411 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5412 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5413 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5414 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5416 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5417 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5418 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5419 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5420 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5422 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5423 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5424 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5425 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5426 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5429 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5430 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5431 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5432 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5433 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5434 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5435 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5436 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5437 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5438 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5439 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5440 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5441 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5442 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5443 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5446 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5447 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5448 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5449 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5450 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5451 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5452 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5453 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5454 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5455 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5456 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5457 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5458 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5459 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5460 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5461 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5462 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5463 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5466 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5467 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5468 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5469 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5470 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5471 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5472 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5473 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5474 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5475 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5476 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5477 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5478 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5479 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5480 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5483 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5484 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5485 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5486 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5487 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5488 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5489 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5490 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5491 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5492 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5493 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5494 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5495 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5496 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5497 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5498 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5499 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5500 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5508 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5509 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5510 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5511 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5512 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5513 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5514 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5515 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5516 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5519 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5520 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5521 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5522 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5523 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5524 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5525 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5526 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5527 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5528 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5529 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5530 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5531 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5532 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5533 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5536 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5537 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5538 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5539 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5540 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5541 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5542 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5543 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5544 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5545 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5546 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5547 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5548 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5549 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5550 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5551 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5552 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5553 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5556 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5557 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5558 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5559 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5560 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5561 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5562 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5563 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5564 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5565 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5566 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5567 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5568 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5569 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5570 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5573 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5574 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5575 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5576 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5577 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5578 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5579 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5580 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5581 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5582 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5583 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5584 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5585 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5586 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5587 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5588 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5589 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5590 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5593 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5594 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5595 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5596 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5597 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5598 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5599 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5600 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5601 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5602 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5603 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5604 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5605 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5606 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5607 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5610 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5611 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5612 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5613 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5614 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5615 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5616 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5617 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5618 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5619 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5620 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5621 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5622 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5623 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5624 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5625 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5626 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5627 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5630 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5631 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5632 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5633 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5634 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5635 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5636 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5637 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5638 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5639 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5640 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM
5641 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5642 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5643 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5644 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5645 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5646 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5647 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5656 case ARM::ADDri: {
5657 if (Inst.getOperand(1).getReg() != ARM::PC ||
5661 TmpInst.setOpcode(ARM::ADR);
5670 case ARM::t2LDRpcrel:
5676 Inst.setOpcode(ARM::tLDRpci);
5678 Inst.setOpcode(ARM::t2LDRpci);
5680 case ARM::t2LDRBpcrel:
5681 Inst.setOpcode(ARM::t2LDRBpci);
5683 case ARM::t2LDRHpcrel:
5684 Inst.setOpcode(ARM::t2LDRHpci);
5686 case ARM::t2LDRSBpcrel:
5687 Inst.setOpcode(ARM::t2LDRSBpci);
5689 case ARM::t2LDRSHpcrel:
5690 Inst.setOpcode(ARM::t2LDRSHpci);
5693 case ARM::VST1LNdWB_register_Asm_8:
5694 case ARM::VST1LNdWB_register_Asm_16:
5695 case ARM::VST1LNdWB_register_Asm_32: {
5713 case ARM::VST2LNdWB_register_Asm_8:
5714 case ARM::VST2LNdWB_register_Asm_16:
5715 case ARM::VST2LNdWB_register_Asm_32:
5716 case ARM::VST2LNqWB_register_Asm_16:
5717 case ARM::VST2LNqWB_register_Asm_32: {
5737 case ARM::VST3LNdWB_register_Asm_8:
5738 case ARM::VST3LNdWB_register_Asm_16:
5739 case ARM::VST3LNdWB_register_Asm_32:
5740 case ARM::VST3LNqWB_register_Asm_16:
5741 case ARM::VST3LNqWB_register_Asm_32: {
5763 case ARM::VST4LNdWB_register_Asm_8:
5764 case ARM::VST4LNdWB_register_Asm_16:
5765 case ARM::VST4LNdWB_register_Asm_32:
5766 case ARM::VST4LNqWB_register_Asm_16:
5767 case ARM::VST4LNqWB_register_Asm_32: {
5791 case ARM::VST1LNdWB_fixed_Asm_8:
5792 case ARM::VST1LNdWB_fixed_Asm_16:
5793 case ARM::VST1LNdWB_fixed_Asm_32: {
5811 case ARM::VST2LNdWB_fixed_Asm_8:
5812 case ARM::VST2LNdWB_fixed_Asm_16:
5813 case ARM::VST2LNdWB_fixed_Asm_32:
5814 case ARM::VST2LNqWB_fixed_Asm_16:
5815 case ARM::VST2LNqWB_fixed_Asm_32: {
5835 case ARM::VST3LNdWB_fixed_Asm_8:
5836 case ARM::VST3LNdWB_fixed_Asm_16:
5837 case ARM::VST3LNdWB_fixed_Asm_32:
5838 case ARM::VST3LNqWB_fixed_Asm_16:
5839 case ARM::VST3LNqWB_fixed_Asm_32: {
5861 case ARM::VST4LNdWB_fixed_Asm_8:
5862 case ARM::VST4LNdWB_fixed_Asm_16:
5863 case ARM::VST4LNdWB_fixed_Asm_32:
5864 case ARM::VST4LNqWB_fixed_Asm_16:
5865 case ARM::VST4LNqWB_fixed_Asm_32: {
5889 case ARM::VST1LNdAsm_8:
5890 case ARM::VST1LNdAsm_16:
5891 case ARM::VST1LNdAsm_32: {
5907 case ARM::VST2LNdAsm_8:
5908 case ARM::VST2LNdAsm_16:
5909 case ARM::VST2LNdAsm_32:
5910 case ARM::VST2LNqAsm_16:
5911 case ARM::VST2LNqAsm_32: {
5929 case ARM::VST3LNdAsm_8:
5930 case ARM::VST3LNdAsm_16:
5931 case ARM::VST3LNdAsm_32:
5932 case ARM::VST3LNqAsm_16:
5933 case ARM::VST3LNqAsm_32: {
5953 case ARM::VST4LNdAsm_8:
5954 case ARM::VST4LNdAsm_16:
5955 case ARM::VST4LNdAsm_32:
5956 case ARM::VST4LNqAsm_16:
5957 case ARM::VST4LNqAsm_32: {
5980 case ARM::VLD1LNdWB_register_Asm_8:
5981 case ARM::VLD1LNdWB_register_Asm_16:
5982 case ARM::VLD1LNdWB_register_Asm_32: {
6001 case ARM::VLD2LNdWB_register_Asm_8:
6002 case ARM::VLD2LNdWB_register_Asm_16:
6003 case ARM::VLD2LNdWB_register_Asm_32:
6004 case ARM::VLD2LNqWB_register_Asm_16:
6005 case ARM::VLD2LNqWB_register_Asm_32: {
6028 case ARM::VLD3LNdWB_register_Asm_8:
6029 case ARM::VLD3LNdWB_register_Asm_16:
6030 case ARM::VLD3LNdWB_register_Asm_32:
6031 case ARM::VLD3LNqWB_register_Asm_16:
6032 case ARM::VLD3LNqWB_register_Asm_32: {
6059 case ARM::VLD4LNdWB_register_Asm_8:
6060 case ARM::VLD4LNdWB_register_Asm_16:
6061 case ARM::VLD4LNdWB_register_Asm_32:
6062 case ARM::VLD4LNqWB_register_Asm_16:
6063 case ARM::VLD4LNqWB_register_Asm_32: {
6094 case ARM::VLD1LNdWB_fixed_Asm_8:
6095 case ARM::VLD1LNdWB_fixed_Asm_16:
6096 case ARM::VLD1LNdWB_fixed_Asm_32: {
6115 case ARM::VLD2LNdWB_fixed_Asm_8:
6116 case ARM::VLD2LNdWB_fixed_Asm_16:
6117 case ARM::VLD2LNdWB_fixed_Asm_32:
6118 case ARM::VLD2LNqWB_fixed_Asm_16:
6119 case ARM::VLD2LNqWB_fixed_Asm_32: {
6142 case ARM::VLD3LNdWB_fixed_Asm_8:
6143 case ARM::VLD3LNdWB_fixed_Asm_16:
6144 case ARM::VLD3LNdWB_fixed_Asm_32:
6145 case ARM::VLD3LNqWB_fixed_Asm_16:
6146 case ARM::VLD3LNqWB_fixed_Asm_32: {
6173 case ARM::VLD4LNdWB_fixed_Asm_8:
6174 case ARM::VLD4LNdWB_fixed_Asm_16:
6175 case ARM::VLD4LNdWB_fixed_Asm_32:
6176 case ARM::VLD4LNqWB_fixed_Asm_16:
6177 case ARM::VLD4LNqWB_fixed_Asm_32: {
6208 case ARM::VLD1LNdAsm_8:
6209 case ARM::VLD1LNdAsm_16:
6210 case ARM::VLD1LNdAsm_32: {
6227 case ARM::VLD2LNdAsm_8:
6228 case ARM::VLD2LNdAsm_16:
6229 case ARM::VLD2LNdAsm_32:
6230 case ARM::VLD2LNqAsm_16:
6231 case ARM::VLD2LNqAsm_32: {
6252 case ARM::VLD3LNdAsm_8:
6253 case ARM::VLD3LNdAsm_16:
6254 case ARM::VLD3LNdAsm_32:
6255 case ARM::VLD3LNqAsm_16:
6256 case ARM::VLD3LNqAsm_32: {
6281 case ARM::VLD4LNdAsm_8:
6282 case ARM::VLD4LNdAsm_16:
6283 case ARM::VLD4LNdAsm_32:
6284 case ARM::VLD4LNqAsm_16:
6285 case ARM::VLD4LNqAsm_32: {
6315 case ARM::VLD3DUPdAsm_8:
6316 case ARM::VLD3DUPdAsm_16:
6317 case ARM::VLD3DUPdAsm_32:
6318 case ARM::VLD3DUPqAsm_8:
6319 case ARM::VLD3DUPqAsm_16:
6320 case ARM::VLD3DUPqAsm_32: {
6337 case ARM::VLD3DUPdWB_fixed_Asm_8:
6338 case ARM::VLD3DUPdWB_fixed_Asm_16:
6339 case ARM::VLD3DUPdWB_fixed_Asm_32:
6340 case ARM::VLD3DUPqWB_fixed_Asm_8:
6341 case ARM::VLD3DUPqWB_fixed_Asm_16:
6342 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6361 case ARM::VLD3DUPdWB_register_Asm_8:
6362 case ARM::VLD3DUPdWB_register_Asm_16:
6363 case ARM::VLD3DUPdWB_register_Asm_32:
6364 case ARM::VLD3DUPqWB_register_Asm_8:
6365 case ARM::VLD3DUPqWB_register_Asm_16:
6366 case ARM::VLD3DUPqWB_register_Asm_32: {
6386 case ARM::VLD3dAsm_8:
6387 case ARM::VLD3dAsm_16:
6388 case ARM::VLD3dAsm_32:
6389 case ARM::VLD3qAsm_8:
6390 case ARM::VLD3qAsm_16:
6391 case ARM::VLD3qAsm_32: {
6408 case ARM::VLD3dWB_fixed_Asm_8:
6409 case ARM::VLD3dWB_fixed_Asm_16:
6410 case ARM::VLD3dWB_fixed_Asm_32:
6411 case ARM::VLD3qWB_fixed_Asm_8:
6412 case ARM::VLD3qWB_fixed_Asm_16:
6413 case ARM::VLD3qWB_fixed_Asm_32: {
6432 case ARM::VLD3dWB_register_Asm_8:
6433 case ARM::VLD3dWB_register_Asm_16:
6434 case ARM::VLD3dWB_register_Asm_32:
6435 case ARM::VLD3qWB_register_Asm_8:
6436 case ARM::VLD3qWB_register_Asm_16:
6437 case ARM::VLD3qWB_register_Asm_32: {
6457 case ARM::VLD4DUPdAsm_8:
6458 case ARM::VLD4DUPdAsm_16:
6459 case ARM::VLD4DUPdAsm_32:
6460 case ARM::VLD4DUPqAsm_8:
6461 case ARM::VLD4DUPqAsm_16:
6462 case ARM::VLD4DUPqAsm_32: {
6481 case ARM::VLD4DUPdWB_fixed_Asm_8:
6482 case ARM::VLD4DUPdWB_fixed_Asm_16:
6483 case ARM::VLD4DUPdWB_fixed_Asm_32:
6484 case ARM::VLD4DUPqWB_fixed_Asm_8:
6485 case ARM::VLD4DUPqWB_fixed_Asm_16:
6486 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6507 case ARM::VLD4DUPdWB_register_Asm_8:
6508 case ARM::VLD4DUPdWB_register_Asm_16:
6509 case ARM::VLD4DUPdWB_register_Asm_32:
6510 case ARM::VLD4DUPqWB_register_Asm_8:
6511 case ARM::VLD4DUPqWB_register_Asm_16:
6512 case ARM::VLD4DUPqWB_register_Asm_32: {
6534 case ARM::VLD4dAsm_8:
6535 case ARM::VLD4dAsm_16:
6536 case ARM::VLD4dAsm_32:
6537 case ARM::VLD4qAsm_8:
6538 case ARM::VLD4qAsm_16:
6539 case ARM::VLD4qAsm_32: {
6558 case ARM::VLD4dWB_fixed_Asm_8:
6559 case ARM::VLD4dWB_fixed_Asm_16:
6560 case ARM::VLD4dWB_fixed_Asm_32:
6561 case ARM::VLD4qWB_fixed_Asm_8:
6562 case ARM::VLD4qWB_fixed_Asm_16:
6563 case ARM::VLD4qWB_fixed_Asm_32: {
6584 case ARM::VLD4dWB_register_Asm_8:
6585 case ARM::VLD4dWB_register_Asm_16:
6586 case ARM::VLD4dWB_register_Asm_32:
6587 case ARM::VLD4qWB_register_Asm_8:
6588 case ARM::VLD4qWB_register_Asm_16:
6589 case ARM::VLD4qWB_register_Asm_32: {
6611 case ARM::VST3dAsm_8:
6612 case ARM::VST3dAsm_16:
6613 case ARM::VST3dAsm_32:
6614 case ARM::VST3qAsm_8:
6615 case ARM::VST3qAsm_16:
6616 case ARM::VST3qAsm_32: {
6633 case ARM::VST3dWB_fixed_Asm_8:
6634 case ARM::VST3dWB_fixed_Asm_16:
6635 case ARM::VST3dWB_fixed_Asm_32:
6636 case ARM::VST3qWB_fixed_Asm_8:
6637 case ARM::VST3qWB_fixed_Asm_16:
6638 case ARM::VST3qWB_fixed_Asm_32: {
6657 case ARM::VST3dWB_register_Asm_8:
6658 case ARM::VST3dWB_register_Asm_16:
6659 case ARM::VST3dWB_register_Asm_32:
6660 case ARM::VST3qWB_register_Asm_8:
6661 case ARM::VST3qWB_register_Asm_16:
6662 case ARM::VST3qWB_register_Asm_32: {
6682 case ARM::VST4dAsm_8:
6683 case ARM::VST4dAsm_16:
6684 case ARM::VST4dAsm_32:
6685 case ARM::VST4qAsm_8:
6686 case ARM::VST4qAsm_16:
6687 case ARM::VST4qAsm_32: {
6706 case ARM::VST4dWB_fixed_Asm_8:
6707 case ARM::VST4dWB_fixed_Asm_16:
6708 case ARM::VST4dWB_fixed_Asm_32:
6709 case ARM::VST4qWB_fixed_Asm_8:
6710 case ARM::VST4qWB_fixed_Asm_16:
6711 case ARM::VST4qWB_fixed_Asm_32: {
6732 case ARM::VST4dWB_register_Asm_8:
6733 case ARM::VST4dWB_register_Asm_16:
6734 case ARM::VST4dWB_register_Asm_32:
6735 case ARM::VST4qWB_register_Asm_8:
6736 case ARM::VST4qWB_register_Asm_16:
6737 case ARM::VST4qWB_register_Asm_32: {
6759 case ARM::t2LSLri:
6760 case ARM::t2LSRri:
6761 case ARM::t2ASRri: {
6764 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6770 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6771 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6772 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6790 case ARM::t2MOVsr:
6791 case ARM::t2MOVSsr: {
6800 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6806 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6807 ARM::tLSRrr : ARM::t2LSRrr; break;
6808 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6809 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6815 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6822 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6826 case ARM::t2MOVsi:
6827 case ARM::t2MOVSsi: {
6834 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6840 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6841 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6842 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6843 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6844 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6852 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6854 if (newOpc != ARM::t2RRX)
6860 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6864 // Handle the ARM mode MOV complex aliases.
6865 case ARM::ASRr:
6866 case ARM::LSRr:
6867 case ARM::LSLr:
6868 case ARM::RORr: {
6872 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6873 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6874 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6875 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6879 TmpInst.setOpcode(ARM::MOVsr);
6890 case ARM::ASRi:
6891 case ARM::LSRi:
6892 case ARM::LSLi:
6893 case ARM::RORi: {
6897 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6898 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6899 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6900 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6904 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6913 if (Opc == ARM::MOVsi)
6921 case ARM::RRXi: {
6924 TmpInst.setOpcode(ARM::MOVsi);
6934 case ARM::t2LDMIA_UPD: {
6936 // a post-indexed LDR instruction instead, per the ARM ARM.
6940 TmpInst.setOpcode(ARM::t2LDR_POST);
6950 case ARM::t2STMDB_UPD: {
6952 // a pre-indexed STR instruction instead, per the ARM ARM.
6956 TmpInst.setOpcode(ARM::t2STR_PRE);
6966 case ARM::LDMIA_UPD:
6968 // a post-indexed LDR instruction instead, per the ARM ARM.
6972 TmpInst.setOpcode(ARM::LDR_POST_IMM);
6984 case ARM::STMDB_UPD:
6986 // a pre-indexed STR instruction instead, per the ARM ARM.
6990 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7000 case ARM::t2ADDri12:
7006 Inst.setOpcode(ARM::t2ADDri);
7009 case ARM::t2SUBri12:
7015 Inst.setOpcode(ARM::t2SUBri);
7018 case ARM::tADDi8:
7020 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7024 Inst.setOpcode(ARM::tADDi3);
7028 case ARM::tSUBi8:
7030 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7034 Inst.setOpcode(ARM::tSUBi3);
7038 case ARM::t2ADDri:
7039 case ARM::t2SUBri: {
7047 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7053 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7054 ARM::tADDi8 : ARM::tSUBi8);
7064 case ARM::t2ADDrr: {
7075 TmpInst.setOpcode(ARM::tADDhirr);
7084 case ARM::tADDrSP: {
7088 Inst.setOpcode(ARM::t2ADDrr);
7094 case ARM::tB:
7097 Inst.setOpcode(ARM::tBcc);
7101 case ARM::t2B:
7104 Inst.setOpcode(ARM::t2Bcc);
7108 case ARM::t2Bcc:
7111 Inst.setOpcode(ARM::t2B);
7115 case ARM::tBcc:
7118 Inst.setOpcode(ARM::tB);
7122 case ARM::tLDMIA: {
7137 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7147 case ARM::tSTMIA_UPD: {
7156 Inst.setOpcode(ARM::t2STMIA_UPD);
7161 case ARM::tPOP: {
7166 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7169 Inst.setOpcode(ARM::t2LDMIA_UPD);
7171 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7172 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7175 case ARM::tPUSH: {
7177 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7180 Inst.setOpcode(ARM::t2STMDB_UPD);
7182 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7183 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7186 case ARM::t2MOVi: {
7192 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7198 TmpInst.setOpcode(ARM::tMOVi8);
7209 case ARM::t2MOVr: {
7215 Inst.getOperand(4).getReg() == ARM::CPSR &&
7220 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7230 case ARM::t2SXTH:
7231 case ARM::t2SXTB:
7232 case ARM::t2UXTH:
7233 case ARM::t2UXTB: {
7244 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7245 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7246 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7247 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7261 case ARM::MOVsi: {
7269 TmpInst.setOpcode(ARM::MOVr);
7280 case ARM::ANDrsi:
7281 case ARM::ORRrsi:
7282 case ARM::EORrsi:
7283 case ARM::BICrsi:
7284 case ARM::SUBrsi:
7285 case ARM::ADDrsi: {
7291 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7292 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7293 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7294 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7295 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7296 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7315 case ARM::ITasm:
7316 case ARM::t2IT: {
7340 case ARM::t2LSLrr:
7341 case ARM::t2LSRrr:
7342 case ARM::t2ASRrr:
7343 case ARM::t2SBCrr:
7344 case ARM::t2RORrr:
7345 case ARM::t2BICrr:
7351 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7352 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7358 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7359 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7360 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7361 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7362 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7363 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7378 case ARM::t2ANDrr:
7379 case ARM::t2EORrr:
7380 case ARM::t2ADCrr:
7381 case ARM::t2ORRrr:
7390 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7391 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7397 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7398 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7399 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7400 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7441 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7445 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7448 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7454 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7459 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7501 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7503 if (Inst.getOpcode() == ARM::ITasm)
7512 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7562 /// parseDirective parses the arm specific directives
7569 else if (IDVal == ".arm")
7646 /// ::= .arm
7653 return Error(L, "target does not support ARM mode");
7712 return Error(L, "'.syntax divided' arm asssembly not supported");
7752 return Error(L, "target does not support ARM mode");
7937 if (NewSPReg != ARM::SP && NewSPReg != FPReg)
