Lines Matching full:arm
1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
10 #define DEBUG_TYPE "arm-disassembler"
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
449 // VFP and NEON instructions, similarly, are shared between ARM
564 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
566 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
571 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
585 case ARM::tBcc:
586 case ARM::t2Bcc:
587 case ARM::tCBZ:
588 case ARM::tCBNZ:
589 case ARM::tCPS:
590 case ARM::t2CPS3p:
591 case ARM::t2CPS2p:
592 case ARM::t2CPS1p:
593 case ARM::tMOVSr:
594 case ARM::tSETEND:
602 case ARM::tB:
603 case ARM::t2B:
604 case ARM::t2TBB:
605 case ARM::t2TBH:
635 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
645 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
651 // encodings between ARM and Thumb modes, and they are predicable in ARM
671 I->setReg(ARM::CPSR);
686 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
687 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
723 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
731 if (MI.getOpcode() == ARM::t2IT) {
852 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
853 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
854 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
855 ARM::R12, ARM::SP, ARM::LR, ARM::PC
888 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
904 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
905 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
928 Register = ARM::R0;
931 Register = ARM::R1;
934 Register = ARM::R2;
937 Register = ARM::R3;
940 Register = ARM::R9;
943 Register = ARM::R12;
963 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
964 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
965 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
966 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
967 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
968 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
969 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
970 ARM::S28, ARM::S29, ARM::S30, ARM::S31
984 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
985 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
986 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
987 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
988 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
989 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
990 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
991 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1020 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1021 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1022 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1023 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1039 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1040 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1041 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1042 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1043 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1044 ARM::Q15
1058 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1059 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1060 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1061 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1062 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1063 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1064 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1065 ARM::D28_D30, ARM::D29_D31
1084 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1090 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1097 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1193 case ARM::LDMIA_UPD:
1194 case ARM::LDMDB_UPD:
1195 case ARM::LDMIB_UPD:
1196 case ARM::LDMDA_UPD:
1197 case ARM::t2LDMIA_UPD:
1198 case ARM::t2LDMDB_UPD:
1307 case ARM::LDC_OFFSET:
1308 case ARM::LDC_PRE:
1309 case ARM::LDC_POST:
1310 case ARM::LDC_OPTION:
1311 case ARM::LDCL_OFFSET:
1312 case ARM::LDCL_PRE:
1313 case ARM::LDCL_POST:
1314 case ARM::LDCL_OPTION:
1315 case ARM::STC_OFFSET:
1316 case ARM::STC_PRE:
1317 case ARM::STC_POST:
1318 case ARM::STC_OPTION:
1319 case ARM::STCL_OFFSET:
1320 case ARM::STCL_PRE:
1321 case ARM::STCL_POST:
1322 case ARM::STCL_OPTION:
1323 case ARM::t2LDC_OFFSET:
1324 case ARM::t2LDC_PRE:
1325 case ARM::t2LDC_POST:
1326 case ARM::t2LDC_OPTION:
1327 case ARM::t2LDCL_OFFSET:
1328 case ARM::t2LDCL_PRE:
1329 case ARM::t2LDCL_POST:
1330 case ARM::t2LDCL_OPTION:
1331 case ARM::t2STC_OFFSET:
1332 case ARM::t2STC_PRE:
1333 case ARM::t2STC_POST:
1334 case ARM::t2STC_OPTION:
1335 case ARM::t2STCL_OFFSET:
1336 case ARM::t2STCL_PRE:
1337 case ARM::t2STCL_POST:
1338 case ARM::t2STCL_OPTION:
1352 case ARM::t2LDC2_OFFSET:
1353 case ARM::t2LDC2L_OFFSET:
1354 case ARM::t2LDC2_PRE:
1355 case ARM::t2LDC2L_PRE:
1356 case ARM::t2STC2_OFFSET:
1357 case ARM::t2STC2L_OFFSET:
1358 case ARM::t2STC2_PRE:
1359 case ARM::t2STC2L_PRE:
1360 case ARM::LDC2_OFFSET:
1361 case ARM::LDC2L_OFFSET:
1362 case ARM::LDC2_PRE:
1363 case ARM::LDC2L_PRE:
1364 case ARM::STC2_OFFSET:
1365 case ARM::STC2L_OFFSET:
1366 case ARM::STC2_PRE:
1367 case ARM::STC2L_PRE:
1368 case ARM::t2LDC_OFFSET:
1369 case ARM::t2LDCL_OFFSET:
1370 case ARM::t2LDC_PRE:
1371 case ARM::t2LDCL_PRE:
1372 case ARM::t2STC_OFFSET:
1373 case ARM::t2STCL_OFFSET:
1374 case ARM::t2STC_PRE:
1375 case ARM::t2STCL_PRE:
1376 case ARM::LDC_OFFSET:
1377 case ARM::LDCL_OFFSET:
1378 case ARM::LDC_PRE:
1379 case ARM::LDCL_PRE:
1380 case ARM::STC_OFFSET:
1381 case ARM::STCL_OFFSET:
1382 case ARM::STC_PRE:
1383 case ARM::STCL_PRE:
1387 case ARM::t2LDC2_POST:
1388 case ARM::t2LDC2L_POST:
1389 case ARM::t2STC2_POST:
1390 case ARM::t2STC2L_POST:
1391 case ARM::LDC2_POST:
1392 case ARM::LDC2L_POST:
1393 case ARM::STC2_POST:
1394 case ARM::STC2L_POST:
1395 case ARM::t2LDC_POST:
1396 case ARM::t2LDCL_POST:
1397 case ARM::t2STC_POST:
1398 case ARM::t2STCL_POST:
1399 case ARM::LDC_POST:
1400 case ARM::LDCL_POST:
1401 case ARM::STC_POST:
1402 case ARM::STCL_POST:
1413 case ARM::LDC_OFFSET:
1414 case ARM::LDC_PRE:
1415 case ARM::LDC_POST:
1416 case ARM::LDC_OPTION:
1417 case ARM::LDCL_OFFSET:
1418 case ARM::LDCL_PRE:
1419 case ARM::LDCL_POST:
1420 case ARM::LDCL_OPTION:
1421 case ARM::STC_OFFSET:
1422 case ARM::STC_PRE:
1423 case ARM::STC_POST:
1424 case ARM::STC_OPTION:
1425 case ARM::STCL_OFFSET:
1426 case ARM::STCL_PRE:
1427 case ARM::STCL_POST:
1428 case ARM::STCL_OPTION:
1455 case ARM::STR_POST_IMM:
1456 case ARM::STR_POST_REG:
1457 case ARM::STRB_POST_IMM:
1458 case ARM::STRB_POST_REG:
1459 case ARM::STRT_POST_REG:
1460 case ARM::STRT_POST_IMM:
1461 case ARM::STRBT_POST_REG:
1462 case ARM::STRBT_POST_IMM:
1475 case ARM::LDR_POST_IMM:
1476 case ARM::LDR_POST_REG:
1477 case ARM::LDRB_POST_IMM:
1478 case ARM::LDRB_POST_REG:
1479 case ARM::LDRBT_POST_REG:
1480 case ARM::LDRBT_POST_IMM:
1481 case ARM::LDRT_POST_REG:
1482 case ARM::LDRT_POST_IMM:
1608 case ARM::STRD:
1609 case ARM::STRD_PRE:
1610 case ARM::STRD_POST:
1611 case ARM::LDRD:
1612 case ARM::LDRD_PRE:
1613 case ARM::LDRD_POST:
1620 case ARM::STRD:
1621 case ARM::STRD_PRE:
1622 case ARM::STRD_POST:
1635 case ARM::STRH:
1636 case ARM::STRH_PRE:
1637 case ARM::STRH_POST:
1645 case ARM::LDRD:
1646 case ARM::LDRD_PRE:
1647 case ARM::LDRD_POST:
1662 case ARM::LDRH:
1663 case ARM::LDRH_PRE:
1664 case ARM::LDRH_POST:
1677 case ARM::LDRSH:
1678 case ARM::LDRSH_PRE:
1679 case ARM::LDRSH_POST:
1680 case ARM::LDRSB:
1681 case ARM::LDRSB_PRE:
1682 case ARM::LDRSB_POST:
1707 case ARM::STRD:
1708 case ARM::STRD_PRE:
1709 case ARM::STRD_POST:
1710 case ARM::STRH:
1711 case ARM::STRH_PRE:
1712 case ARM::STRH_POST:
1724 case ARM::STRD:
1725 case ARM::STRD_PRE:
1726 case ARM::STRD_POST:
1727 case ARM::LDRD:
1728 case ARM::LDRD_PRE:
1729 case ARM::LDRD_POST:
1740 case ARM::LDRD:
1741 case ARM::LDRD_PRE:
1742 case ARM::LDRD_POST:
1743 case ARM::LDRH:
1744 case ARM::LDRH_PRE:
1745 case ARM::LDRH_POST:
1746 case ARM::LDRSH:
1747 case ARM::LDRSH_PRE:
1748 case ARM::LDRSH_POST:
1749 case ARM::LDRSB:
1750 case ARM::LDRSB_PRE:
1751 case ARM::LDRSB_POST:
1752 case ARM::LDRHTr:
1753 case ARM::LDRSBTr:
1844 case ARM::LDMDA:
1845 Inst.setOpcode(ARM::RFEDA);
1847 case ARM::LDMDA_UPD:
1848 Inst.setOpcode(ARM::RFEDA_UPD);
1850 case ARM::LDMDB:
1851 Inst.setOpcode(ARM::RFEDB);
1853 case ARM::LDMDB_UPD:
1854 Inst.setOpcode(ARM::RFEDB_UPD);
1856 case ARM::LDMIA:
1857 Inst.setOpcode(ARM::RFEIA);
1859 case ARM::LDMIA_UPD:
1860 Inst.setOpcode(ARM::RFEIA_UPD);
1862 case ARM::LDMIB:
1863 Inst.setOpcode(ARM::RFEIB);
1865 case ARM::LDMIB_UPD:
1866 Inst.setOpcode(ARM::RFEIB_UPD);
1868 case ARM::STMDA:
1869 Inst.setOpcode(ARM::SRSDA);
1871 case ARM::STMDA_UPD:
1872 Inst.setOpcode(ARM::SRSDA_UPD);
1874 case ARM::STMDB:
1875 Inst.setOpcode(ARM::SRSDB);
1877 case ARM::STMDB_UPD:
1878 Inst.setOpcode(ARM::SRSDB_UPD);
1880 case ARM::STMIA:
1881 Inst.setOpcode(ARM::SRSIA);
1883 case ARM::STMIA_UPD:
1884 Inst.setOpcode(ARM::SRSIA_UPD);
1886 case ARM::STMIB:
1887 Inst.setOpcode(ARM::SRSIB);
1889 case ARM::STMIB_UPD:
1890 Inst.setOpcode(ARM::SRSIB_UPD);
1947 Inst.setOpcode(ARM::CPS3p);
1952 Inst.setOpcode(ARM::CPS2p);
1957 Inst.setOpcode(ARM::CPS1p);
1962 Inst.setOpcode(ARM::CPS1p);
1987 Inst.setOpcode(ARM::t2CPS3p);
1992 Inst.setOpcode(ARM::t2CPS2p);
1997 Inst.setOpcode(ARM::t2CPS1p);
2005 Inst.setOpcode(ARM::t2HINT);
2024 if (Inst.getOpcode() == ARM::t2MOVTi16)
2047 if (Inst.getOpcode() == ARM::MOVTi16)
2171 Inst.setOpcode(ARM::BLXi);
2219 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2220 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2221 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2222 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2223 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2224 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2225 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2226 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2227 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2231 case ARM::VLD2b16:
2232 case ARM::VLD2b32:
2233 case ARM::VLD2b8:
2234 case ARM::VLD2b16wb_fixed:
2235 case ARM::VLD2b16wb_register:
2236 case ARM::VLD2b32wb_fixed:
2237 case ARM::VLD2b32wb_register:
2238 case ARM::VLD2b8wb_fixed:
2239 case ARM::VLD2b8wb_register:
2250 case ARM::VLD3d8:
2251 case ARM::VLD3d16:
2252 case ARM::VLD3d32:
2253 case ARM::VLD3d8_UPD:
2254 case ARM::VLD3d16_UPD:
2255 case ARM::VLD3d32_UPD:
2256 case ARM::VLD4d8:
2257 case ARM::VLD4d16:
2258 case ARM::VLD4d32:
2259 case ARM::VLD4d8_UPD:
2260 case ARM::VLD4d16_UPD:
2261 case ARM::VLD4d32_UPD:
2265 case ARM::VLD3q8:
2266 case ARM::VLD3q16:
2267 case ARM::VLD3q32:
2268 ARM::VLD3q8_UPD:
2269 case ARM::VLD3q16_UPD:
2270 case ARM::VLD3q32_UPD:
2271 case ARM::VLD4q8:
2272 case ARM::VLD4q16:
2273 case ARM::VLD4q32:
2274 case ARM::VLD4q8_UPD:
2275 case ARM::VLD4q16_UPD:
2276 case ARM::VLD4q32_UPD:
2285 case ARM::VLD3d8:
2286 case ARM::VLD3d16:
2287 case ARM::VLD3d32:
2288 case ARM::VLD3d8_UPD:
2289 case ARM::VLD3d16_UPD:
2290 case ARM::VLD3d32_UPD:
2291 case ARM::VLD4d8:
2292 case ARM::VLD4d16:
2293 case ARM::VLD4d32:
2294 case ARM::VLD4d8_UPD:
2295 case ARM::VLD4d16_UPD:
2296 case ARM::VLD4d32_UPD:
2300 case ARM::VLD3q8:
2301 case ARM::VLD3q16:
2302 case ARM::VLD3q32:
2303 case ARM::VLD3q8_UPD:
2304 case ARM::VLD3q16_UPD:
2305 case ARM::VLD3q32_UPD:
2306 case ARM::VLD4q8:
2307 case ARM::VLD4q16:
2308 case ARM::VLD4q32:
2309 case ARM::VLD4q8_UPD:
2310 case ARM::VLD4q16_UPD:
2311 case ARM::VLD4q32_UPD:
2321 case ARM::VLD4d8:
2322 case ARM::VLD4d16:
2323 case ARM::VLD4d32:
2324 case ARM::VLD4d8_UPD:
2325 case ARM::VLD4d16_UPD:
2326 case ARM::VLD4d32_UPD:
2330 case ARM::VLD4q8:
2331 case ARM::VLD4q16:
2332 case ARM::VLD4q32:
2333 case ARM::VLD4q8_UPD:
2334 case ARM::VLD4q16_UPD:
2335 case ARM::VLD4q32_UPD:
2345 case ARM::VLD1d8wb_fixed:
2346 case ARM::VLD1d16wb_fixed:
2347 case ARM::VLD1d32wb_fixed:
2348 case ARM::VLD1d64wb_fixed:
2349 case ARM::VLD1d8wb_register:
2350 case ARM::VLD1d16wb_register:
2351 case ARM::VLD1d32wb_register:
2352 case ARM::VLD1d64wb_register:
2353 case ARM::VLD1q8wb_fixed:
2354 case ARM::VLD1q16wb_fixed:
2355 case ARM::VLD1q32wb_fixed:
2356 case ARM::VLD1q64wb_fixed:
2357 case ARM::VLD1q8wb_register:
2358 case ARM::VLD1q16wb_register:
2359 case ARM::VLD1q32wb_register:
2360 case ARM::VLD1q64wb_register:
2361 case ARM::VLD1d8Twb_fixed:
2362 case ARM::VLD1d8Twb_register:
2363 case ARM::VLD1d16Twb_fixed:
2364 case ARM::VLD1d16Twb_register:
2365 case ARM::VLD1d32Twb_fixed:
2366 case ARM::VLD1d32Twb_register:
2367 case ARM::VLD1d64Twb_fixed:
2368 case ARM::VLD1d64Twb_register:
2369 case ARM::VLD1d8Qwb_fixed:
2370 case ARM::VLD1d8Qwb_register:
2371 case ARM::VLD1d16Qwb_fixed:
2372 case ARM::VLD1d16Qwb_register:
2373 case ARM::VLD1d32Qwb_fixed:
2374 case ARM::VLD1d32Qwb_register:
2375 case ARM::VLD1d64Qwb_fixed:
2376 case ARM::VLD1d64Qwb_register:
2377 case ARM::VLD2d8wb_fixed:
2378 case ARM::VLD2d16wb_fixed:
2379 case ARM::VLD2d32wb_fixed:
2380 case ARM::VLD2q8wb_fixed:
2381 case ARM::VLD2q16wb_fixed:
2382 case ARM::VLD2q32wb_fixed:
2383 case ARM::VLD2d8wb_register:
2384 case ARM::VLD2d16wb_register:
2385 case ARM::VLD2d32wb_register:
2386 case ARM::VLD2q8wb_register:
2387 case ARM::VLD2q16wb_register:
2388 case ARM::VLD2q32wb_register:
2389 case ARM::VLD2b8wb_fixed:
2390 case ARM::VLD2b16wb_fixed:
2391 case ARM::VLD2b32wb_fixed:
2392 case ARM::VLD2b8wb_register:
2393 case ARM::VLD2b16wb_register:
2394 case ARM::VLD2b32wb_register:
2397 case ARM::VLD3d8_UPD:
2398 case ARM::VLD3d16_UPD:
2399 case ARM::VLD3d32_UPD:
2400 case ARM::VLD3q8_UPD:
2401 case ARM::VLD3q16_UPD:
2402 case ARM::VLD3q32_UPD:
2403 case ARM::VLD4d8_UPD:
2404 case ARM::VLD4d16_UPD:
2405 case ARM::VLD4d32_UPD:
2406 case ARM::VLD4q8_UPD:
2407 case ARM::VLD4q16_UPD:
2408 case ARM::VLD4q32_UPD:
2434 case ARM::VLD1d8wb_fixed:
2435 case ARM::VLD1d16wb_fixed:
2436 case ARM::VLD1d32wb_fixed:
2437 case ARM::VLD1d64wb_fixed:
2438 case ARM::VLD1d8Twb_fixed:
2439 case ARM::VLD1d16Twb_fixed:
2440 case ARM::VLD1d32Twb_fixed:
2441 case ARM::VLD1d64Twb_fixed:
2442 case ARM::VLD1d8Qwb_fixed:
2443 case ARM::VLD1d16Qwb_fixed:
2444 case ARM::VLD1d32Qwb_fixed:
2445 case ARM::VLD1d64Qwb_fixed:
2446 case ARM::VLD1d8wb_register:
2447 case ARM::VLD1d16wb_register:
2448 case ARM::VLD1d32wb_register:
2449 case ARM::VLD1d64wb_register:
2450 case ARM::VLD1q8wb_fixed:
2451 case ARM::VLD1q16wb_fixed:
2452 case ARM::VLD1q32wb_fixed:
2453 case ARM::VLD1q64wb_fixed:
2454 case ARM::VLD1q8wb_register:
2455 case ARM::VLD1q16wb_register:
2456 case ARM::VLD1q32wb_register:
2457 case ARM::VLD1q64wb_register:
2465 case ARM::VLD2d8wb_fixed:
2466 case ARM::VLD2d16wb_fixed:
2467 case ARM::VLD2d32wb_fixed:
2468 case ARM::VLD2b8wb_fixed:
2469 case ARM::VLD2b16wb_fixed:
2470 case ARM::VLD2b32wb_fixed:
2471 case ARM::VLD2q8wb_fixed:
2472 case ARM::VLD2q16wb_fixed:
2473 case ARM::VLD2q32wb_fixed:
2544 case ARM::VST1d8wb_fixed:
2545 case ARM::VST1d16wb_fixed:
2546 case ARM::VST1d32wb_fixed:
2547 case ARM::VST1d64wb_fixed:
2548 case ARM::VST1d8wb_register:
2549 case ARM::VST1d16wb_register:
2550 case ARM::VST1d32wb_register:
2551 case ARM::VST1d64wb_register:
2552 case ARM::VST1q8wb_fixed:
2553 case ARM::VST1q16wb_fixed:
2554 case ARM::VST1q32wb_fixed:
2555 case ARM::VST1q64wb_fixed:
2556 case ARM::VST1q8wb_register:
2557 case ARM::VST1q16wb_register:
2558 case ARM::VST1q32wb_register:
2559 case ARM::VST1q64wb_register:
2560 case ARM::VST1d8Twb_fixed:
2561 case ARM::VST1d16Twb_fixed:
2562 case ARM::VST1d32Twb_fixed:
2563 case ARM::VST1d64Twb_fixed:
2564 case ARM::VST1d8Twb_register:
2565 case ARM::VST1d16Twb_register:
2566 case ARM::VST1d32Twb_register:
2567 case ARM::VST1d64Twb_register:
2568 case ARM::VST1d8Qwb_fixed:
2569 case ARM::VST1d16Qwb_fixed:
2570 case ARM::VST1d32Qwb_fixed:
2571 case ARM::VST1d64Qwb_fixed:
2572 case ARM::VST1d8Qwb_register:
2573 case ARM::VST1d16Qwb_register:
2574 case ARM::VST1d32Qwb_register:
2575 case ARM::VST1d64Qwb_register:
2576 case ARM::VST2d8wb_fixed:
2577 case ARM::VST2d16wb_fixed:
2578 case ARM::VST2d32wb_fixed:
2579 case ARM::VST2d8wb_register:
2580 case ARM::VST2d16wb_register:
2581 case ARM::VST2d32wb_register:
2582 case ARM::VST2q8wb_fixed:
2583 case ARM::VST2q16wb_fixed:
2584 case ARM::VST2q32wb_fixed:
2585 case ARM::VST2q8wb_register:
2586 case ARM::VST2q16wb_register:
2587 case ARM::VST2q32wb_register:
2588 case ARM::VST2b8wb_fixed:
2589 case ARM::VST2b16wb_fixed:
2590 case ARM::VST2b32wb_fixed:
2591 case ARM::VST2b8wb_register:
2592 case ARM::VST2b16wb_register:
2593 case ARM::VST2b32wb_register:
2598 case ARM::VST3d8_UPD:
2599 case ARM::VST3d16_UPD:
2600 case ARM::VST3d32_UPD:
2601 case ARM::VST3q8_UPD:
2602 case ARM::VST3q16_UPD:
2603 case ARM::VST3q32_UPD:
2604 case ARM::VST4d8_UPD:
2605 case ARM::VST4d16_UPD:
2606 case ARM::VST4d32_UPD:
2607 case ARM::VST4q8_UPD:
2608 case ARM::VST4q16_UPD:
2609 case ARM::VST4q32_UPD:
2631 case ARM::VST1d8wb_fixed:
2632 case ARM::VST1d16wb_fixed:
2633 case ARM::VST1d32wb_fixed:
2634 case ARM::VST1d64wb_fixed:
2635 case ARM::VST1q8wb_fixed:
2636 case ARM::VST1q16wb_fixed:
2637 case ARM::VST1q32wb_fixed:
2638 case ARM::VST1q64wb_fixed:
2639 case ARM::VST1d8Twb_fixed:
2640 case ARM::VST1d16Twb_fixed:
2641 case ARM::VST1d32Twb_fixed:
2642 case ARM::VST1d64Twb_fixed:
2643 case ARM::VST1d8Qwb_fixed:
2644 case ARM::VST1d16Qwb_fixed:
2645 case ARM::VST1d32Qwb_fixed:
2646 case ARM::VST1d64Qwb_fixed:
2647 case ARM::VST2d8wb_fixed:
2648 case ARM::VST2d16wb_fixed:
2649 case ARM::VST2d32wb_fixed:
2650 case ARM::VST2q8wb_fixed:
2651 case ARM::VST2q16wb_fixed:
2652 case ARM::VST2q32wb_fixed:
2653 case ARM::VST2b8wb_fixed:
2654 case ARM::VST2b16wb_fixed:
2655 case ARM::VST2b32wb_fixed:
2662 case ARM::VST1q16:
2663 case ARM::VST1q32:
2664 case ARM::VST1q64:
2665 case ARM::VST1q8:
2666 case ARM::VST1q16wb_fixed:
2667 case ARM::VST1q16wb_register:
2668 case ARM::VST1q32wb_fixed:
2669 case ARM::VST1q32wb_register:
2670 case ARM::VST1q64wb_fixed:
2671 case ARM::VST1q64wb_register:
2672 case ARM::VST1q8wb_fixed:
2673 case ARM::VST1q8wb_register:
2674 case ARM::VST2d16:
2675 case ARM::VST2d32:
2676 case ARM::VST2d8:
2677 case ARM::VST2d16wb_fixed:
2678 case ARM::VST2d16wb_register:
2679 case ARM::VST2d32wb_fixed:
2680 case ARM::VST2d32wb_register:
2681 case ARM::VST2d8wb_fixed:
2682 case ARM::VST2d8wb_register:
2686 case ARM::VST2b16:
2687 case ARM::VST2b32:
2688 case ARM::VST2b8:
2689 case ARM::VST2b16wb_fixed:
2690 case ARM::VST2b16wb_register:
2691 case ARM::VST2b32wb_fixed:
2692 case ARM::VST2b32wb_register:
2693 case ARM::VST2b8wb_fixed:
2694 case ARM::VST2b8wb_register:
2705 case ARM::VST3d8:
2706 case ARM::VST3d16:
2707 case ARM::VST3d32:
2708 case ARM::VST3d8_UPD:
2709 case ARM::VST3d16_UPD:
2710 case ARM::VST3d32_UPD:
2711 case ARM::VST4d8:
2712 case ARM::VST4d16:
2713 case ARM::VST4d32:
2714 case ARM::VST4d8_UPD:
2715 case ARM::VST4d16_UPD:
2716 case ARM::VST4d32_UPD:
2720 case ARM::VST3q8:
2721 case ARM::VST3q16:
2722 case ARM::VST3q32:
2723 case ARM::VST3q8_UPD:
2724 case ARM::VST3q16_UPD:
2725 case ARM::VST3q32_UPD:
2726 case ARM::VST4q8:
2727 case ARM::VST4q16:
2728 case ARM::VST4q32:
2729 case ARM::VST4q8_UPD:
2730 case ARM::VST4q16_UPD:
2731 case ARM::VST4q32_UPD:
2741 case ARM::VST3d8:
2742 case ARM::VST3d16:
2743 case ARM::VST3d32:
2744 case ARM::VST3d8_UPD:
2745 case ARM::VST3d16_UPD:
2746 case ARM::VST3d32_UPD:
2747 case ARM::VST4d8:
2748 case ARM::VST4d16:
2749 case ARM::VST4d32:
2750 case ARM::VST4d8_UPD:
2751 case ARM::VST4d16_UPD:
2752 case ARM::VST4d32_UPD:
2756 case ARM::VST3q8:
2757 case ARM::VST3q16:
2758 case ARM::VST3q32:
2759 case ARM::VST3q8_UPD:
2760 case ARM::VST3q16_UPD:
2761 case ARM::VST3q32_UPD:
2762 case ARM::VST4q8:
2763 case ARM::VST4q16:
2764 case ARM::VST4q32:
2765 case ARM::VST4q8_UPD:
2766 case ARM::VST4q16_UPD:
2767 case ARM::VST4q32_UPD:
2777 case ARM::VST4d8:
2778 case ARM::VST4d16:
2779 case ARM::VST4d32:
2780 case ARM::VST4d8_UPD:
2781 case ARM::VST4d16_UPD:
2782 case ARM::VST4d32_UPD:
2786 case ARM::VST4q8:
2787 case ARM::VST4q16:
2788 case ARM::VST4q32:
2789 case ARM::VST4q8_UPD:
2790 case ARM::VST4q16_UPD:
2791 case ARM::VST4q32_UPD:
2818 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2819 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2820 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2821 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2862 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2863 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2864 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2865 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2869 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2870 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2871 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2872 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3011 case ARM::VORRiv4i16:
3012 case ARM::VORRiv2i32:
3013 case ARM::VBICiv4i16:
3014 case ARM::VBICiv2i32:
3018 case ARM::VORRiv8i16:
3019 case ARM::VORRiv4i32:
3020 case ARM::VBICiv8i16:
3021 case ARM::VBICiv4i32:
3095 case ARM::VTBL2:
3096 case ARM::VTBX2:
3124 case ARM::tADR:
3126 case ARM::tADDrSPi:
3127 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3200 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3216 case ARM::t2STRHs:
3217 case ARM::t2STRBs:
3218 case ARM::t2STRs:
3243 case ARM::t2LDRBs:
3244 Inst.setOpcode(ARM::t2LDRBpci);
3246 case ARM::t2LDRHs:
3247 Inst.setOpcode(ARM::t2LDRHpci);
3249 case ARM::t2LDRSHs:
3250 Inst.setOpcode(ARM::t2LDRSHpci);
3252 case ARM::t2LDRSBs:
3253 Inst.setOpcode(ARM::t2LDRSBpci);
3255 case ARM::t2LDRs:
3256 Inst.setOpcode(ARM::t2LDRpci);
3258 case ARM::t2PLDs:
3259 Inst.setOpcode(ARM::t2PLDpci);
3261 case ARM::t2PLIs:
3262 Inst.setOpcode(ARM::t2PLIpci);
3273 case ARM::t2LDRSHs:
3275 case ARM::t2LDRHs:
3279 Inst.setOpcode(ARM::t2PLDWs);
3287 case ARM::t2PLDs:
3288 case ARM::t2PLDWs:
3289 case ARM::t2PLIs:
3318 case ARM::t2LDRi8:
3319 Inst.setOpcode(ARM::t2LDRpci);
3321 case ARM::t2LDRBi8:
3322 Inst.setOpcode(ARM::t2LDRBpci);
3324 case ARM::t2LDRSBi8:
3325 Inst.setOpcode(ARM::t2LDRSBpci);
3327 case ARM::t2LDRHi8:
3328 Inst.setOpcode(ARM::t2LDRHpci);
3330 case ARM::t2LDRSHi8:
3331 Inst.setOpcode(ARM::t2LDRSHpci);
3333 case ARM::t2PLDi8:
3334 Inst.setOpcode(ARM::t2PLDpci);
3336 case ARM::t2PLIi8:
3337 Inst.setOpcode(ARM::t2PLIpci);
3347 case ARM::t2LDRSHi8:
3355 case ARM::t2PLDi8:
3356 case ARM::t2PLIi8:
3357 case ARM::t2PLDWi8:
3380 case ARM::t2LDRi12:
3381 Inst.setOpcode(ARM::t2LDRpci);
3383 case ARM::t2LDRHi12:
3384 Inst.setOpcode(ARM::t2LDRHpci);
3386 case ARM::t2LDRSHi12:
3387 Inst.setOpcode(ARM::t2LDRSHpci);
3389 case ARM::t2LDRBi12:
3390 Inst.setOpcode(ARM::t2LDRBpci);
3392 case ARM::t2LDRSBi12:
3393 Inst.setOpcode(ARM::t2LDRSBpci);
3395 case ARM::t2PLDi12:
3396 Inst.setOpcode(ARM::t2PLDpci);
3398 case ARM::t2PLIi12:
3399 Inst.setOpcode(ARM::t2PLIpci);
3409 case ARM::t2LDRSHi12:
3411 case ARM::t2LDRHi12:
3412 Inst.setOpcode(ARM::t2PLDi12);
3420 case ARM::t2PLDi12:
3421 case ARM::t2PLDWi12:
3422 case ARM::t2PLIi12:
3445 case ARM::t2LDRT:
3446 Inst.setOpcode(ARM::t2LDRpci);
3448 case ARM::t2LDRBT:
3449 Inst.setOpcode(ARM::t2LDRBpci);
3451 case ARM::t2LDRHT:
3452 Inst.setOpcode(ARM::t2LDRHpci);
3454 case ARM::t2LDRSBT:
3455 Inst.setOpcode(ARM::t2LDRSBpci);
3457 case ARM::t2LDRSHT:
3458 Inst.setOpcode(ARM::t2LDRSHpci);
3483 case ARM::t2LDRBpci:
3484 case ARM::t2LDRHpci:
3485 Inst.setOpcode(ARM::t2PLDpci);
3487 case ARM::t2LDRSBpci:
3488 Inst.setOpcode(ARM::t2PLIpci);
3490 case ARM::t2LDRSHpci:
3498 case ARM::t2PLDpci:
3499 case ARM::t2PLIpci:
3584 case ARM::t2STRT:
3585 case ARM::t2STRBT:
3586 case ARM::t2STRHT:
3587 case ARM::t2STRi8:
3588 case ARM::t2STRHi8:
3589 case ARM::t2STRBi8:
3599 case ARM::t2LDRT:
3600 case ARM::t2LDRBT:
3601 case ARM::t2LDRHT:
3602 case ARM::t2LDRSBT:
3603 case ARM::t2LDRSHT:
3604 case ARM::t2STRT:
3605 case ARM::t2STRBT:
3606 case ARM::t2STRHT:
3634 case ARM::t2LDR_PRE:
3635 case ARM::t2LDR_POST:
3636 Inst.setOpcode(ARM::t2LDRpci);
3638 case ARM::t2LDRB_PRE:
3639 case ARM::t2LDRB_POST:
3640 Inst.setOpcode(ARM::t2LDRBpci);
3642 case ARM::t2LDRH_PRE:
3643 case ARM::t2LDRH_POST:
3644 Inst.setOpcode(ARM::t2LDRHpci);
3646 case ARM::t2LDRSB_PRE:
3647 case ARM::t2LDRSB_POST:
3649 Inst.setOpcode(ARM::t2PLIpci);
3651 Inst.setOpcode(ARM::t2LDRSBpci);
3653 case ARM::t2LDRSH_PRE:
3654 case ARM::t2LDRSH_POST:
3655 Inst.setOpcode(ARM::t2LDRSHpci);
3691 case ARM::t2STRi12:
3692 case ARM::t2STRBi12:
3693 case ARM::t2STRHi12:
3712 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3713 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3723 if (Inst.getOpcode() == ARM::tADDrSP) {
3729 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3732 } else if (Inst.getOpcode() == ARM::tADDspr) {
3735 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3736 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3809 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3829 Inst.setOpcode(ARM::t2DSB);
3832 Inst.setOpcode(ARM::t2DMB);
3835 Inst.setOpcode(ARM::t2ISB);
4859 Inst.setOpcode(ARM::VMOVv2f32);
4889 Inst.setOpcode(ARM::VMOVv4f32);
