Lines Matching full:arm
27 // stack frame. ARM (especially Thumb) has small immediate offset to
42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
70 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
73 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
123 case ARM::R4:
124 case ARM::R5:
125 case ARM::R6:
126 case ARM::R7:
127 case ARM::LR:
133 case ARM::R8:
134 case ARM::R9:
135 case ARM::R10:
136 case ARM::R11:
153 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
174 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
206 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
207 .addReg(ARM::SP));
224 if (MI->getOpcode() == ARM::tLDRspi &&
228 else if (MI->getOpcode() == ARM::tPOP) {
242 assert((MBBI->getOpcode() == ARM::tBX_RET ||
243 MBBI->getOpcode() == ARM::tPOP_RET) &&
283 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
285 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
287 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
288 ARM::SP)
289 .addReg(ARM::R4));
291 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
292 ARM::SP)
295 if (MBBI->getOpcode() == ARM::tBX_RET &&
297 prior(MBBI)->getOpcode() == ARM::tPOP) {
306 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
315 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
316 .addReg(ARM::R3, RegState::Define);
321 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
322 .addReg(ARM::R3, RegState::Kill);
344 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
353 if (Reg == ARM::LR) {
383 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
389 if (Reg == ARM::LR) {
393 Reg = ARM::PC;
394 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
