Lines Matching full:arm
15 #include "ARM.h"
39 NopInst.setOpcode(ARM::tNOP);
80 if (MBBI->getOpcode() == ARM::t2IT) {
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
141 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
142 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
143 RC == &ARM::GPRnopcRegClass) {
144 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
150 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
155 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
157 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
183 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
184 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
185 RC == &ARM::GPRnopcRegClass) {
186 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
191 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
222 if (DestReg != ARM::SP && DestReg != BaseReg &&
228 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
234 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
243 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
249 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
262 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
264 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
266 BaseReg = ARM::SP;
271 if (BaseReg == ARM::SP) {
273 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
275 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
283 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
295 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
296 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
300 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
329 case ARM::t2LDRi12: return ARM::t2LDRi8;
330 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
331 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
332 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
333 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
334 case ARM::t2STRi12: return ARM::t2STRi8;
335 case ARM::t2STRBi12: return ARM::t2STRBi8;
336 case ARM::t2STRHi12: return ARM::t2STRHi8;
338 case ARM::t2LDRi8:
339 case ARM::t2LDRHi8:
340 case ARM::t2LDRBi8:
341 case ARM::t2LDRSHi8:
342 case ARM::t2LDRSBi8:
343 case ARM::t2STRi8:
344 case ARM::t2STRBi8:
345 case ARM::t2STRHi8:
359 case ARM::t2LDRi8: return ARM::t2LDRi12;
360 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
361 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
362 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
363 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
364 case ARM::t2STRi8: return ARM::t2STRi12;
365 case ARM::t2STRBi8: return ARM::t2STRBi12;
366 case ARM::t2STRHi8: return ARM::t2STRHi12;
368 case ARM::t2LDRi12:
369 case ARM::t2LDRHi12:
370 case ARM::t2LDRBi12:
371 case ARM::t2LDRSHi12:
372 case ARM::t2LDRSBi12:
373 case ARM::t2STRi12:
374 case ARM::t2STRBi12:
375 case ARM::t2STRHi12:
389 case ARM::t2LDRs: return ARM::t2LDRi12;
390 case ARM::t2LDRHs: return ARM::t2LDRHi12;
391 case ARM::t2LDRBs: return ARM::t2LDRBi12;
392 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
393 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
394 case ARM::t2STRs: return ARM::t2STRi12;
395 case ARM::t2STRBs: return ARM::t2STRBi12;
396 case ARM::t2STRHs: return ARM::t2STRHi12;
398 case ARM::t2LDRi12:
399 case ARM::t2LDRHi12:
400 case ARM::t2LDRBi12:
401 case ARM::t2LDRSHi12:
402 case ARM::t2LDRSBi12:
403 case ARM::t2STRi12:
404 case ARM::t2STRBi12:
405 case ARM::t2STRHi12:
406 case ARM::t2LDRi8:
407 case ARM::t2LDRHi8:
408 case ARM::t2LDRBi8:
409 case ARM::t2LDRSHi8:
410 case ARM::t2LDRSBi8:
411 case ARM::t2STRi8:
412 case ARM::t2STRBi8:
413 case ARM::t2STRHi8:
432 if (Opcode == ARM::INLINEASM)
435 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
441 MI.setDesc(TII.get(ARM::tMOVr));
451 bool HasCCOut = Opcode != ARM::t2ADDri12;
456 MI.setDesc(TII.get(ARM::t2SUBri));
458 MI.setDesc(TII.get(ARM::t2ADDri));
474 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
613 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
