Lines Matching defs:CC
457 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
458 switch (CC) {
485 /// conditional moves which use condition code CC should be inverted.
486 static bool invertFPCondCodeUser(Mips::CondCode CC) {
487 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
490 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
513 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
516 DAG.getConstant(condCodeToFCC(CC), MVT::i32));
522 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
523 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
554 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
558 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
1440 Mips::CondCode CC =
1442 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
3136 CallingConv::ID CC, bool IsO32_, CCState &Info,
3138 : CCInfo(Info), CallConv(CC), IsO32(IsO32_),
3347 const MipsCC &CC, const ByValArgInfo &ByVal) const {
3350 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
3355 FrameObjOffset = (int)CC.reservedArgArea() -
3356 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
3370 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
3374 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
3376 unsigned Offset = I * CC.regSize();
3392 const MipsCC &CC, const ByValArgInfo &ByVal,
3396 unsigned RegSize = CC.regSize();
3401 const uint16_t *ArgRegs = CC.intArgRegs();
3485 const MipsCC &CC, SDValue Chain,
3487 unsigned NumRegs = CC.numIntArgRegs();
3488 const uint16_t *ArgRegs = CC.intArgRegs();
3489 const CCState &CCInfo = CC.getCCInfo();
3491 unsigned RegSize = CC.regSize();
3505 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
