Lines Matching defs:Opcode
97 /// rotate and mask opcode and mask operation.
165 /// Reg in an asm, because the load or store opcode would have to change.
325 // opcode and that it has a immediate integer right operand.
366 unsigned Opcode = N->getOpcode();
371 if (Opcode == ISD::SHL) {
376 } else if (Opcode == ISD::SRL) {
383 } else if (Opcode == ISD::ROTL) {
1026 unsigned Opcode;
1033 case MVT::f64: Opcode = PPC::LFDU; break;
1034 case MVT::f32: Opcode = PPC::LFSU; break;
1035 case MVT::i32: Opcode = PPC::LWZU; break;
1036 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
1038 case MVT::i8: Opcode = PPC::LBZU; break;
1045 case MVT::i64: Opcode = PPC::LDU; break;
1046 case MVT::i32: Opcode = PPC::LWZU8; break;
1047 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
1049 case MVT::i8: Opcode = PPC::LBZU8; break;
1056 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1060 unsigned Opcode;
1067 case MVT::f64: Opcode = PPC::LFDUX; break;
1068 case MVT::f32: Opcode = PPC::LFSUX; break;
1069 case MVT::i32: Opcode = PPC::LWZUX; break;
1070 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
1072 case MVT::i8: Opcode = PPC::LBZUX; break;
1080 case MVT::i64: Opcode = PPC::LDUX; break;
1081 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
1082 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
1084 case MVT::i8: Opcode = PPC::LBZUX8; break;
1091 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1457 // inferred from the opcode; when we process it in the AsmPrinter,
