Lines Matching full:x86
1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
10 // This file is part of the X86 Disassembler.
56 namespace X86 {
159 #define ENTRY(x) X86::x,
247 // By default sign-extend all X86 immediates based on their encoding.
255 // Special case those X86 instructions that use the imm8 as a set of
257 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
258 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
259 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
260 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
261 Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
262 Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
263 Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
264 Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
265 Opcode != X86::VINSERTPSrr)
284 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
287 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
290 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
353 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
398 baseReg = MCOperand::CreateReg(X86::x); break;
413 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
414 Opcode == X86::VGATHERDPDYrm ||
415 Opcode == X86::VGATHERQPDrm ||
416 Opcode == X86::VGATHERDPSrm ||
417 Opcode == X86::VGATHERQPSrm ||
418 Opcode == X86::VPGATHERDQrm ||
419 Opcode == X86::VPGATHERDQYrm ||
420 Opcode == X86::VPGATHERQQrm ||
421 Opcode == X86::VPGATHERDDrm ||
422 Opcode == X86::VPGATHERQDrm);
423 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
424 Opcode == X86::VGATHERDPSYrm ||
425 Opcode == X86::VGATHERQPSYrm ||
426 Opcode == X86::VPGATHERQQYrm ||
427 Opcode == X86::VPGATHERDDYrm ||
428 Opcode == X86::VPGATHERQDYrm);
444 indexReg = MCOperand::CreateReg(X86::x); break;
470 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
478 baseReg = MCOperand::CreateReg(X86::BX);
479 indexReg = MCOperand::CreateReg(X86::SI);
482 baseReg = MCOperand::CreateReg(X86::BX);
483 indexReg = MCOperand::CreateReg(X86::DI);
486 baseReg = MCOperand::CreateReg(X86::BP);
487 indexReg = MCOperand::CreateReg(X86::SI);
490 baseReg = MCOperand::CreateReg(X86::BP);
491 indexReg = MCOperand::CreateReg(X86::DI);
505 baseReg = MCOperand::CreateReg(X86::x); break;
524 X86::CS,
525 X86::SS,
526 X86::DS,
527 X86::ES,
528 X86::FS,
529 X86::GS
612 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
695 if(mcInst.getOpcode() == X86::REP_PREFIX)
696 mcInst.setOpcode(X86::XRELEASE_PREFIX);
697 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
698 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
