Lines Matching full:x86
1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
52 return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
59 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
82 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
221 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
222 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
225 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
227 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
236 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
237 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
240 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
242 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
251 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
252 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
255 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
257 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
324 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
329 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
348 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
349 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
370 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
371 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
372 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
373 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
378 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
383 unsigned FixupKind = X86::reloc_riprel_4byte;
388 if (MI.getOpcode() == X86::MOV64rm)
389 FixupKind = X86::reloc_riprel_4byte_movq_load;
420 if (BaseReg == 0) { // [disp32] in X86-32 mode
455 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
461 assert(IndexReg.getReg() != X86::ESP &&
462 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
523 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
704 X86::AddrBaseReg).getReg()))
707 X86::AddrIndexReg).getReg()))
710 X86::AddrIndexReg).getReg()))
713 CurOp += X86::AddrNumOperands;
761 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
764 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
767 X86::AddrIndexReg).getReg()))
775 // CurOp + X86::AddrNumOperands will point to src3.
776 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
796 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
799 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
945 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
947 /// size, and 3) use of X86-64 extended registers.
1008 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
1049 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
1052 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1053 case X86::SS: EmitByte(0x36, CurByte, OS); break;
1054 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1055 case X86::ES: EmitByte(0x26, CurByte, OS); break;
1056 case X86::FS: EmitByte(0x64, CurByte, OS); break;
1057 case X86::GS: EmitByte(0x65, CurByte, OS); break;
1279 SrcRegNum = CurOp + X86::AddrNumOperands;
1316 int AddrOperands = X86::AddrNumOperands;
1361 CurOp += X86::AddrNumOperands;
1435 if (MI.getOpcode() == X86::ADD64ri32 ||
1436 MI.getOpcode() == X86::MOV64ri32 ||
1437 MI.getOpcode() == X86::MOV64mi32 ||
1438 MI.getOpcode() == X86::PUSH64i32)
1439 FixupKind = X86::reloc_signed_4byte;
