Lines Matching full:x86
1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
16 #include "X86.h"
167 // We only handle legal types. For example, on x86-32 the instruction
168 // selector contains all of the 64-bit instructions from x86-64,
188 Opc = X86::MOV8rm;
189 RC = &X86::GR8RegClass;
192 Opc = X86::MOV16rm;
193 RC = &X86::GR16RegClass;
196 Opc = X86::MOV32rm;
197 RC = &X86::GR32RegClass;
200 // Must be in x86-64 mode.
201 Opc = X86::MOV64rm;
202 RC = &X86::GR64RegClass;
206 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
207 RC = &X86::FR32RegClass;
209 Opc = X86::LD_Fp32m;
210 RC = &X86::RFP32RegClass;
215 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
216 RC = &X86::FR64RegClass;
218 Opc = X86::LD_Fp64m;
219 RC = &X86::RFP64RegClass;
247 unsigned AndResult = createResultReg(&X86::GR8RegClass);
249 TII.get(X86::AND8ri), AndResult).addReg(ValReg).addImm(1);
253 case MVT::i8: Opc = X86::MOV8mr; break;
254 case MVT::i16: Opc = X86::MOV16mr; break;
255 case MVT::i32: Opc = X86::MOV32mr; break;
256 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
259 (Subtarget->hasAVX() ? X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m;
263 (Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m;
267 Opc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
269 Opc = Subtarget->hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr;
273 Opc = Subtarget->hasAVX() ? X86::VMOVAPDmr : X86::MOVAPDmr;
275 Opc = Subtarget->hasAVX() ? X86::VMOVUPDmr : X86::MOVUPDmr;
282 Opc = Subtarget->hasAVX() ? X86::VMOVDQAmr : X86::MOVDQAmr;
284 Opc = Subtarget->hasAVX() ? X86::VMOVDQUmr : X86::MOVDQUmr;
306 case MVT::i8: Opc = X86::MOV8mi; break;
307 case MVT::i16: Opc = X86::MOV16mi; break;
308 case MVT::i32: Opc = X86::MOV32mi; break;
312 Opc = X86::MOV64mi32;
536 AM.Base.Reg = X86::RIP;
561 Opc = X86::MOV64rm;
562 RC = &X86::GR64RegClass;
565 StubAM.Base.Reg = X86::RIP;
567 Opc = X86::MOV32rm;
568 RC = &X86::GR32RegClass;
668 AM.Base.Reg = X86::RIP;
784 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
798 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
825 // The x86-64 ABI for returning structs by value requires that we copy
834 unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
878 case MVT::i8: return X86::CMP8rr;
879 case MVT::i16: return X86::CMP16rr;
880 case MVT::i32: return X86::CMP32rr;
881 case MVT::i64: return X86::CMP64rr;
883 return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0;
885 return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0;
896 case MVT::i8: return X86::CMP8ri;
897 case MVT::i16: return X86::CMP16ri;
898 case MVT::i32: return X86::CMP32ri;
903 return X86::CMP64ri32;
948 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
956 unsigned EReg = createResultReg(&X86::GR8RegClass);
957 unsigned NPReg = createResultReg(&X86::GR8RegClass);
958 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
960 TII.get(X86::SETNPr), NPReg);
962 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
970 unsigned NEReg = createResultReg(&X86::GR8RegClass);
971 X86::GR8RegClass);
972 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETNEr), NEReg);
973 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETPr), PReg);
974 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::OR8rr),ResultReg)
979 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
980 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
981 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
982 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
983 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
984 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
985 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
986 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
987 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
988 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
989 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
990 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
992 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
993 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
994 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
995 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
996 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
997 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
998 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
999 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
1000 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
1001 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
1044 case MVT::i8: MovInst = X86::MOVZX32rr8; break;
1045 case MVT::i16: MovInst = X86::MOVZX32rr16; break;
1046 case MVT::i32: MovInst = X86::MOV32rr; break;
1050 unsigned Result32 = createResultReg(&X86::GR32RegClass);
1054 ResultReg = createResultReg(&X86::GR64RegClass);
1057 .addImm(0).addReg(Result32).addImm(X86::sub_32bit);
1092 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
1099 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1100 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1101 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1102 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
1103 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
1104 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1105 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
1106 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
1107 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1108 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
1109 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
1110 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1111 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1113 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1114 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1115 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1116 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1117 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1118 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1119 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
1120 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
1121 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
1122 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
1139 // X86 requires a second branch to handle UNE (and OEQ,
1141 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
1158 case MVT::i8: TestOpc = X86::TEST8ri; break;
1159 case MVT::i16: TestOpc = X86::TEST16ri; break;
1160 case MVT::i32: TestOpc = X86::TEST32ri; break;
1161 case MVT::i64: TestOpc = X86::TEST64ri32; break;
1169 unsigned JmpOpc = X86::JNE_4;
1172 JmpOpc = X86::JE_4;
1190 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
1192 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1203 CReg = X86::CL;
1204 RC = &X86::GR8RegClass;
1206 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1207 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1208 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1212 CReg = X86::CX;
1213 RC = &X86::GR16RegClass;
1215 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1216 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1217 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1221 CReg = X86::ECX;
1222 RC = &X86::GR32RegClass;
1224 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1225 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1226 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1230 CReg = X86::RCX;
1231 RC = &X86::GR64RegClass;
1233 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1234 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1235 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1254 // The shift instruction uses X86::CL. If we defined a super-register
1255 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1256 if (CReg != X86::CL)
1258 TII.get(TargetOpcode::KILL), X86::CL)
1274 // For the X86 DIV/IDIV instruction, in most cases the dividend
1299 { &X86::GR8RegClass, X86::AX, 0, {
1300 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S }, // SDiv
1301 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S }, // SRem
1302 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U }, // UDiv
1303 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U }, // URem
1306 { &X86::GR16RegClass, X86::AX, X86::DX, {
1307 { X86::IDIV16r, X86::CWD, Copy, X86::AX, S }, // SDiv
1308 { X86::IDIV16r, X86::CWD, Copy, X86::DX, S }, // SRem
1309 { X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U }, // UDiv
1310 { X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U }, // URem
1313 { &X86::GR32RegClass, X86::EAX, X86::EDX, {
1314 { X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S }, // SDiv
1315 { X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S }, // SRem
1316 { X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv
1317 { X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U }, // URem
1320 { &X86::GR64RegClass, X86::RAX, X86::RDX, {
1321 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv
1322 { X86::IDIV64r, X86::CQO, Copy, X86::RDX, S }, // SRem
1323 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv
1324 { X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U }, // URem
1371 unsigned Zero32 = createResultReg(&X86::GR32RegClass);
1373 TII.get(X86::MOV32r0), Zero32);
1381 .addReg(Zero32, 0, X86::sub_16bit);
1389 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
1407 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) {
1408 unsigned SourceSuperReg = createResultReg(&X86::GR16RegClass);
1409 unsigned ResultSuperReg = createResultReg(&X86::GR16RegClass);
1411 TII.get(Copy), SourceSuperReg).addReg(X86::AX);
1414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SHR16ri),
1419 /*Kill=*/true, X86::sub_8bit);
1443 Opc = X86::CMOVE16rr;
1444 RC = &X86::GR16RegClass;
1446 Opc = X86::CMOVE32rr;
1447 RC = &X86::GR32RegClass;
1449 Opc = X86::CMOVE64rr;
1450 RC = &X86::GR64RegClass;
1462 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1479 unsigned ResultReg = createResultReg(&X86::FR64RegClass);
1481 TII.get(X86::CVTSS2SDrr), ResultReg)
1498 unsigned ResultReg = createResultReg(&X86::FR32RegClass);
1500 TII.get(X86::CVTSD2SSrr), ResultReg)
1533 // If we're on x86-32; we can't extract an i8 from a general register.
1536 (const TargetRegisterClass*)&X86::GR16_ABCDRegClass :
1537 (const TargetRegisterClass*)&X86::GR32_ABCDRegClass;
1547 X86::sub_8bit);
1670 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1698 OpC = X86::ADD32rr;
1700 OpC = X86::ADD64rr;
1710 unsigned Opc = X86::SETBr;
1712 Opc = X86::SETOr;
1768 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1771 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
1853 x86-32. Special handling for x86-64 is implemented.
1858 if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg,
1930 // calling conventions on x86.
2097 X86::EBX).addReg(Base);
2103 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2104 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2107 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::MOV8ri),
2108 X86::AL).addImm(NumXMMRegs);
2117 CallOpc = X86::CALL64r;
2119 CallOpc = X86::CALL32r;
2128 CallOpc = X86::CALL64pcrel32;
2130 CallOpc = X86::CALLpcrel32;
2135 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2167 MIB.addReg(X86::EBX, RegState::Implicit);
2170 MIB.addReg(X86::AL, RegState::Implicit);
2219 if ((RVLocs[i].getLocReg() == X86::ST0 ||
2220 RVLocs[i].getLocReg() == X86::ST1)) {
2223 CopyReg = createResultReg(&X86::RFP80RegClass);
2225 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL),
2238 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
2244 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
2329 Opc = X86::MOV8rm;
2330 RC = &X86::GR8RegClass;
2333 Opc = X86::MOV16rm;
2334 RC = &X86::GR16RegClass;
2337 Opc = X86::MOV32rm;
2338 RC = &X86::GR32RegClass;
2341 // Must be in x86-64 mode.
2342 Opc = X86::MOV64rm;
2343 RC = &X86::GR64RegClass;
2347 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
2348 RC = &X86::FR32RegClass;
2350 Opc = X86::LD_Fp32m;
2351 RC = &X86::RFP32RegClass;
2356 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
2357 RC = &X86::FR64RegClass;
2359 Opc = X86::LD_Fp64m;
2360 RC = &X86::RFP64RegClass;
2378 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
2394 // x86-32 PIC requires a PIC base register for constant pools.
2405 PICBase = X86::RIP;
2432 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
2452 Opc = X86::FsFLD0SS;
2453 RC = &X86::FR32RegClass;
2455 Opc = X86::LD_Fp032;
2456 RC = &X86::RFP32RegClass;
2461 Opc = X86::FsFLD0SD;
2462 RC = &X86::FR64RegClass;
2464 Opc = X86::LD_Fp064;
2465 RC = &X86::RFP64RegClass;
2504 FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo,
