Lines Matching defs:Lower
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
662 // Lower this to FGETSIGNx86 plus an AND.
967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
970 // Do not attempt to custom lower non-power-of-2 vectors
973 // Do not attempt to custom lower non-128-bit vectors
1015 // Custom lower v2i64 and v2f64 selects.
1224 // Don't lower v32i8 because there is no 128-bit byte mul
1243 // Don't lower v32i8 because there is no 128-bit byte mul
1256 // Custom lower several nodes for 256-bit types.
1266 // Do not attempt to custom lower other non-256-bit vectors
1394 // Custom lower several nodes.
1408 // Do not attempt to custom lower other non-512-bit vectors
1452 // We want to custom lower some of our intrinsics.
1456 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1630 // Do not use f64 to lower memcpy if source is string constant. It's
1936 /// LowerCallResult - Lower the result values of a call into the
2534 // Lower arguments at fp - stackoffset + fpdiff.
2681 // For tail calls lower the arguments to the 'real' stack slot.
2954 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3549 // Lower quadword copied in order or undef.
3559 // Lower quadword copied in order or undef.
3582 // Lower quadword shuffled.
3592 // Lower quadword shuffled.
4506 /// match movhlps. The lower half elements should come from upper half of
4561 /// match movlp{s|d}. The lower half elements should come from lower half of
4774 // refer to the higher part, which is a duplication of the lower one,
5131 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5179 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5605 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5903 // Build both the lower and upper subvector.
5904 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5908 // Recreate the wider vector with the lower and upper part.
5909 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6069 // Try to lower a shuffle node into a simple blend instruction.
7173 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7434 // lower it into other known shuffles. FIXME: this isn't true yet, but
7611 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7756 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7782 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
8040 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8054 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8101 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8185 // Darwin only has one model of TLS. Lower to that.
8297 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8351 "Unknown SINT_TO_FP to lower!");
8670 "Unknown FP_TO_INT to lower!");
8681 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8693 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8705 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8761 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8763 // Concat upper and lower parts.
8766 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8768 // Concat upper and lower parts.
9163 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9756 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9763 // bits of the inputs before performing those operations. The lower
9800 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9809 // Make sure the lower and upper halves are both all-ones.
9855 // Lower (X & (1 << N)) == 0 to BT(X, N).
9856 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9857 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9949 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10487 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10750 default: return SDValue(); // Don't custom lower most intrinsics.
11083 // return an integer value, not just an instruction so lower it to the ptest
11393 default: return SDValue(); // Don't custom lower most intrinsics.
11892 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
11895 "Should not custom lower when pmuldq is available!");
11917 "Only know how to lower V2I64/V4I64 multiply");
11960 // Lower sdiv X, pow2-const.
12333 // Lower SHL with variable shift amount.
12430 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12800 default: llvm_unreachable("Should not custom lower this!");
13290 // If lower 4G is not available, then we must use rip-relative addressing.
13850 // Use pseudo select and lower them.
17643 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
17664 // Otherwise, lower to two pairs of 32-bit loads / stores.
18553 // lower so don't worry about this.
18783 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
