Lines Matching defs:Opcode
2981 unsigned Opcode = Def->getOpcode();
2982 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3235 static bool isTargetShuffle(unsigned Opcode) {
3236 switch(Opcode) {
4847 /// target specific opcode. Returns true if the Mask could be calculated.
4936 unsigned Opcode = V.getOpcode();
4952 if (isTargetShuffle(Opcode)) {
4972 if (Opcode == ISD::BITCAST) {
7756 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7782 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
9293 unsigned Opcode = 0;
9344 Opcode = X86ISD::INC;
9351 Opcode = X86ISD::DEC;
9358 Opcode = X86ISD::ADD;
9400 case ISD::SUB: Opcode = X86ISD::SUB; break;
9401 case ISD::XOR: Opcode = X86ISD::XOR; break;
9402 case ISD::AND: Opcode = X86ISD::AND; break;
9409 Opcode = X86ISD::OR;
9436 // Use a target machine opcode to prevent further DAGCombine
9458 if (Opcode == 0)
9468 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9899 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9961 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
9962 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10721 // Change opcode to non-immediate version
10883 unsigned Opcode;
10890 Opcode = X86ISD::FHADD;
10896 Opcode = X86ISD::FHSUB;
10902 Opcode = X86ISD::HADD;
10908 Opcode = X86ISD::HSUB;
10911 return DAG.getNode(Opcode, dl, Op.getValueType(),
10940 unsigned Opcode;
10949 Opcode = X86ISD::UMAX;
10957 Opcode = X86ISD::UMIN;
10965 Opcode = X86ISD::SMAX;
10973 Opcode = X86ISD::SMIN;
10976 return DAG.getNode(Opcode, dl, Op.getValueType(),
10989 unsigned Opcode;
10996 Opcode = X86ISD::FMAX;
11002 Opcode = X86ISD::FMIN;
11005 return DAG.getNode(Opcode, dl, Op.getValueType(),
11020 unsigned Opcode;
11027 Opcode = ISD::SHL;
11033 Opcode = ISD::SRL;
11037 Opcode = ISD::SRA;
11040 return DAG.getNode(Opcode, dl, Op.getValueType(),
11165 unsigned Opcode;
11174 Opcode = X86ISD::VSHL;
11182 Opcode = X86ISD::VSRL;
11188 Opcode = X86ISD::VSRA;
11191 return DAG.getNode(Opcode, dl, Op.getValueType(),
11212 unsigned Opcode;
11221 Opcode = X86ISD::VSHLI;
11229 Opcode = X86ISD::VSRLI;
11235 Opcode = X86ISD::VSRAI;
11238 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11252 unsigned Opcode;
11257 Opcode = X86ISD::PCMPISTRI;
11261 Opcode = X86ISD::PCMPESTRI;
11265 Opcode = X86ISD::PCMPISTRI;
11269 Opcode = X86ISD::PCMPESTRI;
11273 Opcode = X86ISD::PCMPISTRI;
11277 Opcode = X86ISD::PCMPESTRI;
11281 Opcode = X86ISD::PCMPISTRI;
11285 Opcode = X86ISD::PCMPESTRI;
11289 Opcode = X86ISD::PCMPISTRI;
11293 Opcode = X86ISD::PCMPESTRI;
11299 Opcode, dl, VTs, NewOps.data(), NewOps.size());
11308 unsigned Opcode;
11310 Opcode = X86ISD::PCMPISTRI;
11312 Opcode = X86ISD::PCMPESTRI;
11316 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11402 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11408 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11554 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
11555 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
11563 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
11565 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11577 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11580 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11591 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11594 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11658 // This is storing the opcode for MOV32ri.
11659 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11672 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12066 llvm_unreachable("Unknown shift opcode.");
12110 llvm_unreachable("Unknown shift opcode.");
12148 llvm_unreachable("Unknown shift opcode!");
12233 llvm_unreachable("Unknown shift opcode!");
12287 llvm_unreachable("Unknown shift opcode!");
13035 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13037 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13063 default: llvm_unreachable("Unexpected opcode");
13106 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13107 switch (Opcode) {
13520 // Get CMPXCHG opcode for the specified data type.
13533 // Get LOAD opcode for the specified data type.
13546 // Get opcode of the non-atomic one from the specified atomic instruction.
13562 llvm_unreachable("Unhandled atomic-load-op opcode!");
13565 // Get opcode of the non-atomic one from the specified atomic instruction with
13566 // extra opcode.
13591 llvm_unreachable("Unhandled atomic-load-op opcode!");
13594 // Get opcode of the non-atomic one from the specified atomic instruction for
13609 llvm_unreachable("Unhandled atomic-load-op opcode!");
13612 // Get opcode of the non-atomic one from the specified atomic instruction for
13613 // 64-bit data type on 32-bit target with extra opcode.
13623 llvm_unreachable("Unhandled atomic-load-op opcode!");
13626 // Get pseudo CMOV opcode from the specified data type.
13635 llvm_unreachable("Unknown CMOV opcode!");
13762 llvm_unreachable("Unhandled atomic-load-op opcode!");
14066 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14206 default: llvm_unreachable("illegal opcode!");
14243 default: llvm_unreachable("illegal opcode!");
14673 // true/false values to select between, and a branch opcode to use.
15241 // Get the X86 opcode to use.
15244 default: llvm_unreachable("illegal opcode!");
15940 unsigned Opcode = 0;
15956 Opcode = X86ISD::FMIN;
15964 Opcode = X86ISD::FMIN;
15973 Opcode = X86ISD::FMIN;
15982 Opcode = X86ISD::FMAX;
15994 Opcode = X86ISD::FMAX;
16003 Opcode = X86ISD::FMAX;
16021 Opcode = X86ISD::FMIN;
16028 Opcode = X86ISD::FMIN;
16037 Opcode = X86ISD::FMIN;
16044 Opcode = X86ISD::FMAX;
16056 Opcode = X86ISD::FMAX;
16065 Opcode = X86ISD::FMAX;
16070 if (Opcode)
16071 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16799 unsigned opcode;
16803 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
16963 unsigned Opcode = N->getOpcode();
16964 switch (Opcode) {
16978 llvm_unreachable("Unexpected opcode");
17889 default: llvm_unreachable("unknown opcode");
18041 unsigned Opcode;
18043 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18045 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18047 return DAG.getNode(Opcode, dl, VT, A, B, C);
