Lines Matching full:pshuflw
3240 case X86ISD::PSHUFLW:
3280 case X86ISD::PSHUFLW:
3573 /// is suitable for input to PSHUFLW.
4347 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4887 case X86ISD::PSHUFLW:
6126 // 1. [all] pshuflw, pshufhw, optional move
6129 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6223 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6233 pshuflw = false;
6241 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6243 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6244 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6304 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6323 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
7376 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
13223 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18398 case X86ISD::PSHUFLW:
