Lines Matching refs:i1
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
1343 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1405 if (VT.getVectorElementType() == MVT::i1)
1927 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
5610 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5615 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5623 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5716 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
13337 // truncation all the way down to i1 is valid.
16407 // truncated to i1 using 'and'.
18936 if (VT == MVT::i8 || VT == MVT::i1)
18948 if (VT == MVT::i8 || VT == MVT::i1)
18955 if (VT == MVT::i8 || VT == MVT::i1)
18963 if (VT == MVT::i8 || VT == MVT::i1)
19077 if (VT == MVT::i8 || VT == MVT::i1) {
