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  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
radeon_variable.h 46 struct rc_dst_register Dst;
  /external/llvm/include/llvm/Target/
CostTable.h 44 TypeTy Dst;
52 unsigned len, int ISD, TypeTy Dst, TypeTy Src) {
54 if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)
  /external/llvm/lib/Target/R600/MCTargetDesc/
AMDGPUAsmBackend.cpp 76 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
78 *Dst = (Value - 4) / 4;
  /external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_variable.h 46 struct rc_dst_register Dst;
  /external/llvm/lib/Support/
ConvertUTFWrapper.cpp 114 UTF8 *Dst = reinterpret_cast<UTF8 *>(&Out[0]);
115 UTF8 *DstEnd = Dst + Out.size();
118 ConvertUTF16toUTF8(&Src, SrcEnd, &Dst, DstEnd, strictConversion);
126 Out.resize(reinterpret_cast<char *>(Dst) - &Out[0]);
  /external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp 103 const MCOperand &Dst = MI->getOperand(0);
113 printRegName(O, Dst.getReg());
126 const MCOperand &Dst = MI->getOperand(0);
135 printRegName(O, Dst.getReg());
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 103 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
139 MachineOperand &Dst = MI->getOperand(0);
141 unsigned DstReg = Dst.getReg();
158 MachineOperand &Dst = MI->getOperand(0);
163 unsigned DstReg = Dst.getReg();
175 MachineOperand &Dst = MI->getOperand(0);
180 unsigned DstReg = Dst.getReg();
190 MachineOperand &Dst = MI->getOperand(0);
192 unsigned DstReg = Dst.getReg();
208 MachineOperand &Dst = MI->getOperand(0)
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcInstrInfo.cpp 292 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
294 assert(Dst && Src && "Bad sub-register");
296 MovMI = BuildMI(MBB, I, DL, get(SP::FMOVS), Dst).addReg(Src);
  /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/
tgsi_parse.h 99 struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS];
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/tests/
rc_test_helpers.c 227 fprintf(stderr, "Failed to execute regex for dst register.\n");
245 fprintf(stderr, "Unknown dst register file type.\n");
254 fprintf(stderr, "Could not convert dst register index\n");
287 DBG("Dst Reg File=%u Index=%d Writemask=%d\n",
299 struct match_info Dst;
353 tokens.Dst.String = inst_str + matches[3].rm_so;
354 tokens.Dst.Length = match_length(matches, 3);
357 dst_str = malloc(sizeof(char) * (tokens.Dst.Length + 1));
358 strncpy(dst_str, tokens.Dst.String, tokens.Dst.Length)
    [all...]
  /external/clang/lib/StaticAnalyzer/Core/
CoreEngine.cpp 274 ExplodedNodeSet &Dst) {
278 Dst.Add(*I);
457 ExplodedNodeSet Dst;
458 SubEng.processBranch(Cond, Term, Ctx, Pred, Dst,
461 enqueue(Dst);
469 ExplodedNodeSet Dst;
470 SubEng.processStaticInitializer(DS, Ctx, Pred, Dst,
473 enqueue(Dst);
ExprEngineCXX.cpp 27 ExplodedNodeSet &Dst) {
28 StmtNodeBuilder Bldr(Pred, Dst, *currBldrCtx);
58 ExplodedNodeSet Dst;
71 evalBind(Dst, CallExpr, Pred, ThisVal, V, true);
74 for (ExplodedNodeSet::iterator I = Dst.begin(), E = Dst.end();
286 ExplodedNodeSet &Dst) {
320 getCheckerManager().runCheckersForPostCall(Dst, DstInvalidated,
325 ExplodedNodeSet &Dst) {
381 StmtNodeBuilder Bldr(Pred, Dst, *currBldrCtx)
    [all...]
ExprEngineCallAndReturn.cpp 161 ExplodedNodeSet &Dst) {
167 Dst.Add(Pred);
178 removeDead(Pred, Dst, dyn_cast<ReturnStmt>(LastSt), LCtx,
322 // CEENode -> Dst -> WorkList
335 ExplodedNodeSet Dst;
337 getCheckerManager().runCheckersForPostObjCMessage(Dst, DstPostCall, *Msg,
341 getCheckerManager().runCheckersForPostStmt(Dst, DstPostCall, CE,
344 Dst.insert(DstPostCall);
348 for (ExplodedNodeSet::iterator PSI = Dst.begin(), PSE = Dst.end()
    [all...]
  /external/llvm/lib/Target/R600/
R600Packetizer.cpp 83 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
87 unsigned Dst = BI->getOperand(DstIdx).getReg();
89 Result[Dst] = AMDGPU::PS;
94 Result[Dst] = AMDGPU::PV_X;
97 if (Dst == AMDGPU::OQAP) {
101 switch (TRI.getHWRegChan(Dst)) {
117 Result[Dst] = PVReg;
SILowerControlFlow.cpp 196 unsigned Dst = MI.getOperand(0).getReg();
200 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
205 .addReg(Dst);
216 unsigned Dst = MI.getOperand(0).getReg();
219 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
230 unsigned Dst = MI.getOperand(0).getReg();
234 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
245 unsigned Dst = MI.getOperand(0).getReg();
249 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
377 unsigned Dst = MI.getOperand(0).getReg()
    [all...]
  /external/mesa3d/src/gallium/auxiliary/tgsi/
tgsi_parse.h 99 struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS];
  /external/mesa3d/src/gallium/drivers/r300/compiler/tests/
rc_test_helpers.c 227 fprintf(stderr, "Failed to execute regex for dst register.\n");
245 fprintf(stderr, "Unknown dst register file type.\n");
254 fprintf(stderr, "Could not convert dst register index\n");
287 DBG("Dst Reg File=%u Index=%d Writemask=%d\n",
299 struct match_info Dst;
353 tokens.Dst.String = inst_str + matches[3].rm_so;
354 tokens.Dst.Length = match_length(matches, 3);
357 dst_str = malloc(sizeof(char) * (tokens.Dst.Length + 1));
358 strncpy(dst_str, tokens.Dst.String, tokens.Dst.Length)
    [all...]
  /external/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp 48 bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
125 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
128 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
169 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
170 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
171 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
211 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
213 if (Mips::ACRegsDSPRegClass.contains(Dst, Src))
214 return expandCopyACC(MBB, I, Dst, Src, 4);
216 if (Mips::ACRegs128RegClass.contains(Dst, Src)
    [all...]
MipsSEInstrInfo.cpp 407 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
408 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/
i915_fpc.h 303 struct i915_full_dst_register Dst[1];
  /external/llvm/include/llvm/Analysis/
DependenceAnalysis.h 75 Dst(Destination),
108 Instruction *getDst() const { return Dst; }
204 Instruction *Src, *Dst;
221 Instruction *Dst,
284 /// depends - Tests for a dependence between the Src and Dst instructions.
288 /// if it appears that control flow can reach from Src to Dst
291 Instruction *Dst,
347 const SCEV *Dst;
459 /// establishNestingLevels - Examines the loop nesting of the Src and Dst
476 /// ... - loops containing Src but not Dst
    [all...]
  /external/llvm/lib/CodeGen/
TailDuplication.cpp 282 unsigned Dst = Copy->getOperand(0).getReg();
285 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
287 MRI->replaceRegWith(Dst, Src);
    [all...]
  /external/mesa3d/src/gallium/drivers/i915/
i915_fpc.h 303 struct i915_full_dst_register Dst[1];
  /external/clang/lib/CodeGen/
MicrosoftCXXABI.cpp     [all...]
  /external/llvm/lib/ExecutionEngine/
ExecutionEngine.cpp     [all...]

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