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      1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Sparc implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "SparcInstrInfo.h"
     15 #include "Sparc.h"
     16 #include "SparcMachineFunctionInfo.h"
     17 #include "SparcSubtarget.h"
     18 #include "llvm/ADT/STLExtras.h"
     19 #include "llvm/ADT/SmallVector.h"
     20 #include "llvm/CodeGen/MachineFrameInfo.h"
     21 #include "llvm/CodeGen/MachineInstrBuilder.h"
     22 #include "llvm/CodeGen/MachineMemOperand.h"
     23 #include "llvm/CodeGen/MachineRegisterInfo.h"
     24 #include "llvm/Support/ErrorHandling.h"
     25 #include "llvm/Support/TargetRegistry.h"
     26 
     27 #define GET_INSTRINFO_CTOR
     28 #include "SparcGenInstrInfo.inc"
     29 
     30 using namespace llvm;
     31 
     32 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
     33   : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
     34     RI(ST), Subtarget(ST) {
     35 }
     36 
     37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
     38 /// load from a stack slot, return the virtual or physical register number of
     39 /// the destination along with the FrameIndex of the loaded stack slot.  If
     40 /// not, return 0.  This predicate must return 0 if the instruction has
     41 /// any side effects other than loading from the stack slot.
     42 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
     43                                              int &FrameIndex) const {
     44   if (MI->getOpcode() == SP::LDri ||
     45       MI->getOpcode() == SP::LDXri ||
     46       MI->getOpcode() == SP::LDFri ||
     47       MI->getOpcode() == SP::LDDFri) {
     48     if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
     49         MI->getOperand(2).getImm() == 0) {
     50       FrameIndex = MI->getOperand(1).getIndex();
     51       return MI->getOperand(0).getReg();
     52     }
     53   }
     54   return 0;
     55 }
     56 
     57 /// isStoreToStackSlot - If the specified machine instruction is a direct
     58 /// store to a stack slot, return the virtual or physical register number of
     59 /// the source reg along with the FrameIndex of the loaded stack slot.  If
     60 /// not, return 0.  This predicate must return 0 if the instruction has
     61 /// any side effects other than storing to the stack slot.
     62 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
     63                                             int &FrameIndex) const {
     64   if (MI->getOpcode() == SP::STri ||
     65       MI->getOpcode() == SP::STXri ||
     66       MI->getOpcode() == SP::STFri ||
     67       MI->getOpcode() == SP::STDFri) {
     68     if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
     69         MI->getOperand(1).getImm() == 0) {
     70       FrameIndex = MI->getOperand(0).getIndex();
     71       return MI->getOperand(2).getReg();
     72     }
     73   }
     74   return 0;
     75 }
     76 
     77 static bool IsIntegerCC(unsigned CC)
     78 {
     79   return  (CC <= SPCC::ICC_VC);
     80 }
     81 
     82 
     83 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
     84 {
     85   switch(CC) {
     86   case SPCC::ICC_NE:   return SPCC::ICC_E;
     87   case SPCC::ICC_E:    return SPCC::ICC_NE;
     88   case SPCC::ICC_G:    return SPCC::ICC_LE;
     89   case SPCC::ICC_LE:   return SPCC::ICC_G;
     90   case SPCC::ICC_GE:   return SPCC::ICC_L;
     91   case SPCC::ICC_L:    return SPCC::ICC_GE;
     92   case SPCC::ICC_GU:   return SPCC::ICC_LEU;
     93   case SPCC::ICC_LEU:  return SPCC::ICC_GU;
     94   case SPCC::ICC_CC:   return SPCC::ICC_CS;
     95   case SPCC::ICC_CS:   return SPCC::ICC_CC;
     96   case SPCC::ICC_POS:  return SPCC::ICC_NEG;
     97   case SPCC::ICC_NEG:  return SPCC::ICC_POS;
     98   case SPCC::ICC_VC:   return SPCC::ICC_VS;
     99   case SPCC::ICC_VS:   return SPCC::ICC_VC;
    100 
    101   case SPCC::FCC_U:    return SPCC::FCC_O;
    102   case SPCC::FCC_O:    return SPCC::FCC_U;
    103   case SPCC::FCC_G:    return SPCC::FCC_LE;
    104   case SPCC::FCC_LE:   return SPCC::FCC_G;
    105   case SPCC::FCC_UG:   return SPCC::FCC_ULE;
    106   case SPCC::FCC_ULE:  return SPCC::FCC_UG;
    107   case SPCC::FCC_L:    return SPCC::FCC_GE;
    108   case SPCC::FCC_GE:   return SPCC::FCC_L;
    109   case SPCC::FCC_UL:   return SPCC::FCC_UGE;
    110   case SPCC::FCC_UGE:  return SPCC::FCC_UL;
    111   case SPCC::FCC_LG:   return SPCC::FCC_UE;
    112   case SPCC::FCC_UE:   return SPCC::FCC_LG;
    113   case SPCC::FCC_NE:   return SPCC::FCC_E;
    114   case SPCC::FCC_E:    return SPCC::FCC_NE;
    115   }
    116   llvm_unreachable("Invalid cond code");
    117 }
    118 
    119 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
    120                                    MachineBasicBlock *&TBB,
    121                                    MachineBasicBlock *&FBB,
    122                                    SmallVectorImpl<MachineOperand> &Cond,
    123                                    bool AllowModify) const
    124 {
    125 
    126   MachineBasicBlock::iterator I = MBB.end();
    127   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
    128   while (I != MBB.begin()) {
    129     --I;
    130 
    131     if (I->isDebugValue())
    132       continue;
    133 
    134     // When we see a non-terminator, we are done.
    135     if (!isUnpredicatedTerminator(I))
    136       break;
    137 
    138     // Terminator is not a branch.
    139     if (!I->isBranch())
    140       return true;
    141 
    142     // Handle Unconditional branches.
    143     if (I->getOpcode() == SP::BA) {
    144       UnCondBrIter = I;
    145 
    146       if (!AllowModify) {
    147         TBB = I->getOperand(0).getMBB();
    148         continue;
    149       }
    150 
    151       while (llvm::next(I) != MBB.end())
    152         llvm::next(I)->eraseFromParent();
    153 
    154       Cond.clear();
    155       FBB = 0;
    156 
    157       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
    158         TBB = 0;
    159         I->eraseFromParent();
    160         I = MBB.end();
    161         UnCondBrIter = MBB.end();
    162         continue;
    163       }
    164 
    165       TBB = I->getOperand(0).getMBB();
    166       continue;
    167     }
    168 
    169     unsigned Opcode = I->getOpcode();
    170     if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
    171       return true; // Unknown Opcode.
    172 
    173     SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
    174 
    175     if (Cond.empty()) {
    176       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
    177       if (AllowModify && UnCondBrIter != MBB.end() &&
    178           MBB.isLayoutSuccessor(TargetBB)) {
    179 
    180         // Transform the code
    181         //
    182         //    brCC L1
    183         //    ba L2
    184         // L1:
    185         //    ..
    186         // L2:
    187         //
    188         // into
    189         //
    190         //   brnCC L2
    191         // L1:
    192         //   ...
    193         // L2:
    194         //
    195         BranchCode = GetOppositeBranchCondition(BranchCode);
    196         MachineBasicBlock::iterator OldInst = I;
    197         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
    198           .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
    199         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
    200           .addMBB(TargetBB);
    201 
    202         OldInst->eraseFromParent();
    203         UnCondBrIter->eraseFromParent();
    204 
    205         UnCondBrIter = MBB.end();
    206         I = MBB.end();
    207         continue;
    208       }
    209       FBB = TBB;
    210       TBB = I->getOperand(0).getMBB();
    211       Cond.push_back(MachineOperand::CreateImm(BranchCode));
    212       continue;
    213     }
    214     // FIXME: Handle subsequent conditional branches.
    215     // For now, we can't handle multiple conditional branches.
    216     return true;
    217   }
    218   return false;
    219 }
    220 
    221 unsigned
    222 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
    223                              MachineBasicBlock *FBB,
    224                              const SmallVectorImpl<MachineOperand> &Cond,
    225                              DebugLoc DL) const {
    226   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
    227   assert((Cond.size() == 1 || Cond.size() == 0) &&
    228          "Sparc branch conditions should have one component!");
    229 
    230   if (Cond.empty()) {
    231     assert(!FBB && "Unconditional branch with multiple successors!");
    232     BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
    233     return 1;
    234   }
    235 
    236   // Conditional branch
    237   unsigned CC = Cond[0].getImm();
    238 
    239   if (IsIntegerCC(CC))
    240     BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
    241   else
    242     BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
    243   if (!FBB)
    244     return 1;
    245 
    246   BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
    247   return 2;
    248 }
    249 
    250 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
    251 {
    252   MachineBasicBlock::iterator I = MBB.end();
    253   unsigned Count = 0;
    254   while (I != MBB.begin()) {
    255     --I;
    256 
    257     if (I->isDebugValue())
    258       continue;
    259 
    260     if (I->getOpcode() != SP::BA
    261         && I->getOpcode() != SP::BCOND
    262         && I->getOpcode() != SP::FBCOND)
    263       break; // Not a branch
    264 
    265     I->eraseFromParent();
    266     I = MBB.end();
    267     ++Count;
    268   }
    269   return Count;
    270 }
    271 
    272 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
    273                                  MachineBasicBlock::iterator I, DebugLoc DL,
    274                                  unsigned DestReg, unsigned SrcReg,
    275                                  bool KillSrc) const {
    276   if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
    277     BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
    278       .addReg(SrcReg, getKillRegState(KillSrc));
    279   else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
    280     BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
    281       .addReg(SrcReg, getKillRegState(KillSrc));
    282   else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
    283     if (Subtarget.isV9()) {
    284       BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
    285         .addReg(SrcReg, getKillRegState(KillSrc));
    286     } else {
    287       // Use two FMOVS instructions.
    288       const TargetRegisterInfo *TRI = &getRegisterInfo();
    289       MachineInstr *MovMI = 0;
    290       unsigned subRegIdx[] = {SP::sub_even, SP::sub_odd};
    291       for (unsigned i = 0; i != 2; ++i) {
    292         unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
    293         unsigned Src = TRI->getSubReg(SrcReg,  subRegIdx[i]);
    294         assert(Dst && Src && "Bad sub-register");
    295 
    296         MovMI = BuildMI(MBB, I, DL, get(SP::FMOVS), Dst).addReg(Src);
    297       }
    298       // Add implicit super-register defs and kills to the last MovMI.
    299       MovMI->addRegisterDefined(DestReg, TRI);
    300       if (KillSrc)
    301         MovMI->addRegisterKilled(SrcReg, TRI);
    302     }
    303   } else
    304     llvm_unreachable("Impossible reg-to-reg copy");
    305 }
    306 
    307 void SparcInstrInfo::
    308 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
    309                     unsigned SrcReg, bool isKill, int FI,
    310                     const TargetRegisterClass *RC,
    311                     const TargetRegisterInfo *TRI) const {
    312   DebugLoc DL;
    313   if (I != MBB.end()) DL = I->getDebugLoc();
    314 
    315   MachineFunction *MF = MBB.getParent();
    316   const MachineFrameInfo &MFI = *MF->getFrameInfo();
    317   MachineMemOperand *MMO =
    318     MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
    319                              MachineMemOperand::MOStore,
    320                              MFI.getObjectSize(FI),
    321                              MFI.getObjectAlignment(FI));
    322 
    323   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
    324   if (RC == &SP::I64RegsRegClass)
    325     BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
    326       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
    327   else if (RC == &SP::IntRegsRegClass)
    328     BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
    329       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
    330   else if (RC == &SP::FPRegsRegClass)
    331     BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
    332       .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
    333   else if (RC == &SP::DFPRegsRegClass)
    334     BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
    335       .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
    336   else
    337     llvm_unreachable("Can't store this register to stack slot");
    338 }
    339 
    340 void SparcInstrInfo::
    341 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
    342                      unsigned DestReg, int FI,
    343                      const TargetRegisterClass *RC,
    344                      const TargetRegisterInfo *TRI) const {
    345   DebugLoc DL;
    346   if (I != MBB.end()) DL = I->getDebugLoc();
    347 
    348   MachineFunction *MF = MBB.getParent();
    349   const MachineFrameInfo &MFI = *MF->getFrameInfo();
    350   MachineMemOperand *MMO =
    351     MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
    352                              MachineMemOperand::MOLoad,
    353                              MFI.getObjectSize(FI),
    354                              MFI.getObjectAlignment(FI));
    355 
    356   if (RC == &SP::I64RegsRegClass)
    357     BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
    358       .addMemOperand(MMO);
    359   else if (RC == &SP::IntRegsRegClass)
    360     BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
    361       .addMemOperand(MMO);
    362   else if (RC == &SP::FPRegsRegClass)
    363     BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
    364       .addMemOperand(MMO);
    365   else if (RC == &SP::DFPRegsRegClass)
    366     BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
    367       .addMemOperand(MMO);
    368   else
    369     llvm_unreachable("Can't load this register from stack slot");
    370 }
    371 
    372 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
    373 {
    374   SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
    375   unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
    376   if (GlobalBaseReg != 0)
    377     return GlobalBaseReg;
    378 
    379   // Insert the set of GlobalBaseReg into the first MBB of the function
    380   MachineBasicBlock &FirstMBB = MF->front();
    381   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
    382   MachineRegisterInfo &RegInfo = MF->getRegInfo();
    383 
    384   GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
    385 
    386 
    387   DebugLoc dl;
    388 
    389   BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
    390   SparcFI->setGlobalBaseReg(GlobalBaseReg);
    391   return GlobalBaseReg;
    392 }
    393