| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode();
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 93 unsigned Opcode = Node->getOpcode();
110 switch(Opcode) {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZMCInstLower.cpp | 18 // If Opcode is an interprocedural reference that can be shortened,
20 static unsigned getShortenedInstr(unsigned Opcode) {
21 switch (Opcode) {
24 return Opcode;
96 unsigned Opcode = MI->getOpcode();
100 Opcode = getShortenedInstr(Opcode);
101 OutMI.setOpcode(Opcode);
|
| SystemZRegisterInfo.cpp | 84 unsigned Opcode = MI->getOpcode();
85 unsigned OpcodeForOffset = TII.getOpcodeForOffset(Opcode, Offset);
95 OpcodeForOffset = TII.getOpcodeForOffset(Opcode, Offset);
|
| /external/smack/src/org/xbill/DNS/ |
| Opcode.java | 11 public final class Opcode {
30 private static Mnemonic opcodes = new Mnemonic("DNS Opcode",
46 Opcode() {}
48 /** Converts a numeric Opcode into a String */
54 /** Converts a String representation of an Opcode into its numeric value */
|
| /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/Format/ |
| OffsetInstructionFormatMethodItem.java | 35 import org.jf.dexlib.Code.Opcode;
70 if (instruction.opcode == Opcode.FILL_ARRAY_DATA) {
73 if (instruction.opcode == Opcode.PACKED_SWITCH) {
76 assert instruction.opcode == Opcode.SPARSE_SWITCH;
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 150 int Opcode = InstIn.getOpcode();
152 if (Opcode == Mips::DEXT)
169 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
175 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
209 unsigned Opcode = TmpInst.getOpcode();
210 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
211 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
214 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
216 Opcode = NewOpcode
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 90 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
94 const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode);
145 unsigned Opcode = MI->getOpcode();
148 GetInstrType(Opcode, isFirst, isSingle, isCracked,
182 if (HasCTRSet && Opcode == PPC::BCTRL)
203 unsigned Opcode = MI->getOpcode();
206 GetInstrType(Opcode, isFirst, isSingle, isCracked,
211 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 171 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
172 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
180 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
181 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
|
| SparcInstrInfo.cpp | 169 unsigned Opcode = I->getOpcode();
170 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
171 return true; // Unknown Opcode.
197 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCAsmBackend.cpp | 38 // If Opcode is a relaxable interprocedural reference, return the relaxed form,
40 static unsigned getRelaxedOpcode(unsigned Opcode) {
41 switch (Opcode) {
133 unsigned Opcode = getRelaxedOpcode(Inst.getOpcode());
134 assert(Opcode && "Unexpected insn to relax");
136 Res.setOpcode(Opcode);
|
| /external/smali/dexlib/src/main/java/org/jf/dexlib/Code/Format/ |
| Instruction21h.java | 33 import org.jf.dexlib.Code.Opcode;
44 public Instruction21h(Opcode opcode, short regA, short litB) {
45 super(opcode);
55 private Instruction21h(Opcode opcode, byte[] buffer, int bufferIndex) {
56 super(opcode);
63 out.writeByte(opcode.value);
81 if (opcode == Opcode.CONST_HIGH16)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 133 unsigned Opcode;
137 Opcode = AMDGPU::CUBE_r600_real;
140 Opcode = AMDGPU::CUBE_eg_real;
144 Opcode = 0;
148 Opcode = MI.getOpcode();
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
|
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| prog_instruction.c | 144 gl_inst_opcode Opcode;
152 * \note Opcode should equal array index!
254 * Return the number of src registers for the given instruction/opcode.
257 _mesa_num_inst_src_regs(gl_inst_opcode opcode)
259 ASSERT(opcode < MAX_OPCODE);
260 ASSERT(opcode == InstInfo[opcode].Opcode);
261 ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
262 return InstInfo[opcode].NumSrcRegs
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 77 unsigned Opcode = MI->getOpcode();
80 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
94 if (Opcode == ARM::t2HINT)
101 if (Opcode == ARM::MOVsr) {
124 if (Opcode == ARM::MOVsi) {
154 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
160 if (Opcode == ARM::t2STMDB_UPD)
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 83 unsigned Opcode = MI.getOpcode();
84 if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
85 Opcode == PPC::BL8_NOP_TLS)
|
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 69 unsigned Opcode;
106 Opcode = AMDGPU::S_MOV_B32;
111 Opcode = AMDGPU::S_MOV_B32;
116 Opcode = AMDGPU::S_MOV_B32;
129 Opcode = AMDGPU::V_MOV_B32_e32;
134 Opcode = AMDGPU::V_MOV_B32_e32;
140 Opcode = AMDGPU::V_MOV_B32_e32;
146 Opcode = AMDGPU::V_MOV_B32_e32;
152 Opcode = AMDGPU::V_MOV_B32_e32;
161 get(Opcode), RI.getSubReg(DestReg, SubIdx))
[all...] |
| R600EmitClauseMarkers.cpp | 200 unsigned Opcode = PushBeforeModifier ?
202 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
|
| R600ExpandSpecialInstrs.cpp | 76 // The native opcode used by PRED_X is stored as an immediate in the
79 MI.getOperand(2).getImm(), // opcode
192 unsigned Opcode = BMI->getOpcode();
196 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
199 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
288 unsigned Opcode = MI.getOpcode();
289 switch (Opcode) {
291 Opcode = AMDGPU::CUBE_r600_real;
294 Opcode = AMDGPU::CUBE_eg_real;
301 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 133 unsigned Opcode;
137 Opcode = AMDGPU::CUBE_r600_real;
140 Opcode = AMDGPU::CUBE_eg_real;
144 Opcode = 0;
148 Opcode = MI.getOpcode();
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
|
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.c | 144 gl_inst_opcode Opcode;
152 * \note Opcode should equal array index!
254 * Return the number of src registers for the given instruction/opcode.
257 _mesa_num_inst_src_regs(gl_inst_opcode opcode)
259 ASSERT(opcode < MAX_OPCODE);
260 ASSERT(opcode == InstInfo[opcode].Opcode);
261 ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
262 return InstInfo[opcode].NumSrcRegs
[all...] |
| /external/chromium_org/third_party/WebKit/Source/core/xml/ |
| XPathPredicate.h | 65 enum Opcode {
68 NumericOp(Opcode, Expression* lhs, Expression* rhs);
73 Opcode m_opcode;
78 enum Opcode { OP_EQ, OP_NE, OP_GT, OP_LT, OP_GE, OP_LE };
79 EqTestOp(Opcode, Expression* lhs, Expression* rhs);
85 Opcode m_opcode;
90 enum Opcode { OP_And, OP_Or };
91 LogicalOp(Opcode, Expression* lhs, Expression* rhs);
97 Opcode m_opcode;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_program_pair.h | 72 unsigned int Opcode:8;
|
| /external/chromium_org/third_party/mesa/src/src/mesa/main/ |
| atifragshader.h | 24 GLenum opcode; member in struct:ati_fs_opcode_st
53 GLenum Opcode[2];
62 GLenum Opcode;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXGenericToNVVM.cpp | 308 unsigned Opcode = C->getOpcode();
309 switch (Opcode) {
351 if (Instruction::isBinaryOp(Opcode)) {
356 if (Instruction::isCast(Opcode)) {
|
