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      1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef X86SUBTARGET_H
     15 #define X86SUBTARGET_H
     16 
     17 #include "llvm/ADT/Triple.h"
     18 #include "llvm/IR/CallingConv.h"
     19 #include "llvm/Target/TargetSubtargetInfo.h"
     20 #include <string>
     21 
     22 #define GET_SUBTARGETINFO_HEADER
     23 #include "X86GenSubtargetInfo.inc"
     24 
     25 namespace llvm {
     26 class GlobalValue;
     27 class StringRef;
     28 class TargetMachine;
     29 
     30 /// PICStyles - The X86 backend supports a number of different styles of PIC.
     31 ///
     32 namespace PICStyles {
     33 enum Style {
     34   StubPIC,          // Used on i386-darwin in -fPIC mode.
     35   StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
     36   GOT,              // Used on many 32-bit unices in -fPIC mode.
     37   RIPRel,           // Used on X86-64 when not in -static mode.
     38   None              // Set when in -static mode (not PIC or DynamicNoPIC mode).
     39 };
     40 }
     41 
     42 class X86Subtarget : public X86GenSubtargetInfo {
     43 protected:
     44   enum X86SSEEnum {
     45     NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512
     46   };
     47 
     48   enum X863DNowEnum {
     49     NoThreeDNow, ThreeDNow, ThreeDNowA
     50   };
     51 
     52   enum X86ProcFamilyEnum {
     53     Others, IntelAtom
     54   };
     55 
     56   /// X86ProcFamily - X86 processor family: Intel Atom, and others
     57   X86ProcFamilyEnum X86ProcFamily;
     58 
     59   /// PICStyle - Which PIC style to use
     60   ///
     61   PICStyles::Style PICStyle;
     62 
     63   /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
     64   /// none supported.
     65   X86SSEEnum X86SSELevel;
     66 
     67   /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
     68   ///
     69   X863DNowEnum X863DNowLevel;
     70 
     71   /// HasCMov - True if this processor has conditional move instructions
     72   /// (generally pentium pro+).
     73   bool HasCMov;
     74 
     75   /// HasX86_64 - True if the processor supports X86-64 instructions.
     76   ///
     77   bool HasX86_64;
     78 
     79   /// HasPOPCNT - True if the processor supports POPCNT.
     80   bool HasPOPCNT;
     81 
     82   /// HasSSE4A - True if the processor supports SSE4A instructions.
     83   bool HasSSE4A;
     84 
     85   /// HasAES - Target has AES instructions
     86   bool HasAES;
     87 
     88   /// HasPCLMUL - Target has carry-less multiplication
     89   bool HasPCLMUL;
     90 
     91   /// HasFMA - Target has 3-operand fused multiply-add
     92   bool HasFMA;
     93 
     94   /// HasFMA4 - Target has 4-operand fused multiply-add
     95   bool HasFMA4;
     96 
     97   /// HasXOP - Target has XOP instructions
     98   bool HasXOP;
     99 
    100   /// HasMOVBE - True if the processor has the MOVBE instruction.
    101   bool HasMOVBE;
    102 
    103   /// HasRDRAND - True if the processor has the RDRAND instruction.
    104   bool HasRDRAND;
    105 
    106   /// HasF16C - Processor has 16-bit floating point conversion instructions.
    107   bool HasF16C;
    108 
    109   /// HasFSGSBase - Processor has FS/GS base insturctions.
    110   bool HasFSGSBase;
    111 
    112   /// HasLZCNT - Processor has LZCNT instruction.
    113   bool HasLZCNT;
    114 
    115   /// HasBMI - Processor has BMI1 instructions.
    116   bool HasBMI;
    117 
    118   /// HasBMI2 - Processor has BMI2 instructions.
    119   bool HasBMI2;
    120 
    121   /// HasRTM - Processor has RTM instructions.
    122   bool HasRTM;
    123 
    124   /// HasHLE - Processor has HLE.
    125   bool HasHLE;
    126 
    127   /// HasADX - Processor has ADX instructions.
    128   bool HasADX;
    129 
    130   /// HasPRFCHW - Processor has PRFCHW instructions.
    131   bool HasPRFCHW;
    132 
    133   /// HasRDSEED - Processor has RDSEED instructions.
    134   bool HasRDSEED;
    135 
    136   /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
    137   bool IsBTMemSlow;
    138 
    139   /// IsUAMemFast - True if unaligned memory access is fast.
    140   bool IsUAMemFast;
    141 
    142   /// HasVectorUAMem - True if SIMD operations can have unaligned memory
    143   /// operands. This may require setting a feature bit in the processor.
    144   bool HasVectorUAMem;
    145 
    146   /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
    147   /// this is true for most x86-64 chips, but not the first AMD chips.
    148   bool HasCmpxchg16b;
    149 
    150   /// UseLeaForSP - True if the LEA instruction should be used for adjusting
    151   /// the stack pointer. This is an optimization for Intel Atom processors.
    152   bool UseLeaForSP;
    153 
    154   /// HasSlowDivide - True if smaller divides are significantly faster than
    155   /// full divides and should be used when possible.
    156   bool HasSlowDivide;
    157 
    158   /// PostRAScheduler - True if using post-register-allocation scheduler.
    159   bool PostRAScheduler;
    160 
    161   /// PadShortFunctions - True if the short functions should be padded to prevent
    162   /// a stall when returning too early.
    163   bool PadShortFunctions;
    164 
    165   /// CallRegIndirect - True if the Calls with memory reference should be converted
    166   /// to a register-based indirect call.
    167   bool CallRegIndirect;
    168   /// LEAUsesAG - True if the LEA instruction inputs have to be ready at
    169   ///             address generation (AG) time.
    170   bool LEAUsesAG;
    171 
    172   /// Processor has AVX-512 PreFetch Instructions
    173   bool HasPFI;
    174 
    175   /// Processor has AVX-512 Exponential and Reciprocal Instructions
    176   bool HasERI;
    177 
    178   /// Processor has AVX-512 Conflict Detection Instructions
    179   bool HasCDI;
    180 
    181   /// stackAlignment - The minimum alignment known to hold of the stack frame on
    182   /// entry to the function and which must be maintained by every function.
    183   unsigned stackAlignment;
    184 
    185   /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
    186   ///
    187   unsigned MaxInlineSizeThreshold;
    188 
    189   /// TargetTriple - What processor and OS we're targeting.
    190   Triple TargetTriple;
    191 
    192   /// Instruction itineraries for scheduling
    193   InstrItineraryData InstrItins;
    194 
    195 private:
    196   /// StackAlignOverride - Override the stack alignment.
    197   unsigned StackAlignOverride;
    198 
    199   /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
    200   bool In64BitMode;
    201 
    202 public:
    203   /// This constructor initializes the data members to match that
    204   /// of the specified triple.
    205   ///
    206   X86Subtarget(const std::string &TT, const std::string &CPU,
    207                const std::string &FS,
    208                unsigned StackAlignOverride, bool is64Bit);
    209 
    210   /// getStackAlignment - Returns the minimum alignment known to hold of the
    211   /// stack frame on entry to the function and which must be maintained by every
    212   /// function for this subtarget.
    213   unsigned getStackAlignment() const { return stackAlignment; }
    214 
    215   /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
    216   /// that still makes it profitable to inline the call.
    217   unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
    218 
    219   /// ParseSubtargetFeatures - Parses features string setting specified
    220   /// subtarget options.  Definition of function is auto generated by tblgen.
    221   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
    222 
    223   /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
    224   /// instruction.
    225   void AutoDetectSubtargetFeatures();
    226 
    227   /// \brief Reset the features for the X86 target.
    228   virtual void resetSubtargetFeatures(const MachineFunction *MF);
    229 private:
    230   void initializeEnvironment();
    231   void resetSubtargetFeatures(StringRef CPU, StringRef FS);
    232 public:
    233   /// Is this x86_64? (disregarding specific ABI / programming model)
    234   bool is64Bit() const {
    235     return In64BitMode;
    236   }
    237 
    238   /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
    239   bool isTarget64BitILP32() const {
    240     return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32);
    241   }
    242 
    243   /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
    244   bool isTarget64BitLP64() const {
    245     return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32);
    246   }
    247 
    248   PICStyles::Style getPICStyle() const { return PICStyle; }
    249   void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
    250 
    251   bool hasCMov() const { return HasCMov; }
    252   bool hasMMX() const { return X86SSELevel >= MMX; }
    253   bool hasSSE1() const { return X86SSELevel >= SSE1; }
    254   bool hasSSE2() const { return X86SSELevel >= SSE2; }
    255   bool hasSSE3() const { return X86SSELevel >= SSE3; }
    256   bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
    257   bool hasSSE41() const { return X86SSELevel >= SSE41; }
    258   bool hasSSE42() const { return X86SSELevel >= SSE42; }
    259   bool hasAVX() const { return X86SSELevel >= AVX; }
    260   bool hasAVX2() const { return X86SSELevel >= AVX2; }
    261   bool hasAVX512() const { return X86SSELevel >= AVX512; }
    262   bool hasFp256() const { return hasAVX(); }
    263   bool hasInt256() const { return hasAVX2(); }
    264   bool hasSSE4A() const { return HasSSE4A; }
    265   bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
    266   bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
    267   bool hasPOPCNT() const { return HasPOPCNT; }
    268   bool hasAES() const { return HasAES; }
    269   bool hasPCLMUL() const { return HasPCLMUL; }
    270   bool hasFMA() const { return HasFMA; }
    271   // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
    272   bool hasFMA4() const { return HasFMA4 && !HasFMA; }
    273   bool hasXOP() const { return HasXOP; }
    274   bool hasMOVBE() const { return HasMOVBE; }
    275   bool hasRDRAND() const { return HasRDRAND; }
    276   bool hasF16C() const { return HasF16C; }
    277   bool hasFSGSBase() const { return HasFSGSBase; }
    278   bool hasLZCNT() const { return HasLZCNT; }
    279   bool hasBMI() const { return HasBMI; }
    280   bool hasBMI2() const { return HasBMI2; }
    281   bool hasRTM() const { return HasRTM; }
    282   bool hasHLE() const { return HasHLE; }
    283   bool hasADX() const { return HasADX; }
    284   bool hasPRFCHW() const { return HasPRFCHW; }
    285   bool hasRDSEED() const { return HasRDSEED; }
    286   bool isBTMemSlow() const { return IsBTMemSlow; }
    287   bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
    288   bool hasVectorUAMem() const { return HasVectorUAMem; }
    289   bool hasCmpxchg16b() const { return HasCmpxchg16b; }
    290   bool useLeaForSP() const { return UseLeaForSP; }
    291   bool hasSlowDivide() const { return HasSlowDivide; }
    292   bool padShortFunctions() const { return PadShortFunctions; }
    293   bool callRegIndirect() const { return CallRegIndirect; }
    294   bool LEAusesAG() const { return LEAUsesAG; }
    295   bool hasCDI() const { return HasCDI; }
    296   bool hasPFI() const { return HasPFI; }
    297   bool hasERI() const { return HasERI; }
    298 
    299   bool isAtom() const { return X86ProcFamily == IntelAtom; }
    300 
    301   const Triple &getTargetTriple() const { return TargetTriple; }
    302 
    303   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
    304   bool isTargetFreeBSD() const {
    305     return TargetTriple.getOS() == Triple::FreeBSD;
    306   }
    307   bool isTargetSolaris() const {
    308     return TargetTriple.getOS() == Triple::Solaris;
    309   }
    310   bool isTargetELF() const {
    311     return (TargetTriple.getEnvironment() == Triple::ELF ||
    312             TargetTriple.isOSBinFormatELF());
    313   }
    314   bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
    315   bool isTargetNaCl() const {
    316     return TargetTriple.getOS() == Triple::NaCl;
    317   }
    318   bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
    319   bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
    320   bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
    321   bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
    322   bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
    323   bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
    324   bool isTargetCOFF() const {
    325     return (TargetTriple.getEnvironment() != Triple::ELF &&
    326             TargetTriple.isOSBinFormatCOFF());
    327   }
    328   bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
    329 
    330   bool isTargetWin64() const {
    331     // FIXME: x86_64-cygwin has not been released yet.
    332     return In64BitMode && TargetTriple.isOSWindows();
    333   }
    334 
    335   bool isTargetWin32() const {
    336     // FIXME: Cygwin is included for isTargetWin64 -- should it be included
    337     // here too?
    338     return !In64BitMode && (isTargetMingw() || isTargetWindows());
    339   }
    340 
    341   bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
    342   bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
    343   bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
    344 
    345   bool isPICStyleStubPIC() const {
    346     return PICStyle == PICStyles::StubPIC;
    347   }
    348 
    349   bool isPICStyleStubNoDynamic() const {
    350     return PICStyle == PICStyles::StubDynamicNoPIC;
    351   }
    352   bool isPICStyleStubAny() const {
    353     return PICStyle == PICStyles::StubDynamicNoPIC ||
    354            PICStyle == PICStyles::StubPIC;
    355   }
    356 
    357   bool isCallingConvWin64(CallingConv::ID CC) const {
    358     return (isTargetWin64() && CC != CallingConv::X86_64_SysV) ||
    359            CC == CallingConv::X86_64_Win64;
    360   }
    361 
    362   /// ClassifyGlobalReference - Classify a global variable reference for the
    363   /// current subtarget according to how we should reference it in a non-pcrel
    364   /// context.
    365   unsigned char ClassifyGlobalReference(const GlobalValue *GV,
    366                                         const TargetMachine &TM)const;
    367 
    368   /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
    369   /// current subtarget according to how we should reference it in a non-pcrel
    370   /// context.
    371   unsigned char ClassifyBlockAddressReference() const;
    372 
    373   /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
    374   /// to immediate address.
    375   bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
    376 
    377   /// This function returns the name of a function which has an interface
    378   /// like the non-standard bzero function, if such a function exists on
    379   /// the current subtarget and it is considered prefereable over
    380   /// memset with zero passed as the second argument. Otherwise it
    381   /// returns null.
    382   const char *getBZeroEntry() const;
    383 
    384   /// This function returns true if the target has sincos() routine in its
    385   /// compiler runtime or math libraries.
    386   bool hasSinCos() const;
    387 
    388   /// enablePostRAScheduler - run for Atom optimization.
    389   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
    390                              TargetSubtargetInfo::AntiDepBreakMode& Mode,
    391                              RegClassVector& CriticalPathRCs) const;
    392 
    393   bool postRAScheduler() const { return PostRAScheduler; }
    394 
    395   /// getInstrItins = Return the instruction itineraries based on the
    396   /// subtarget selection.
    397   const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
    398 };
    399 
    400 } // End llvm namespace
    401 
    402 #endif
    403