| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 85 int DestReg = MI->getOperand(0).getReg();
89 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
91 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
98 int DestReg = MI->getOperand(0).getReg();
102 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
104 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
111 int DestReg = MI->getOperand(0).getReg();
115 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
117 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
124 int DestReg = MI->getOperand(0).getReg()
[all...] |
| HexagonSplitTFRCondSets.cpp | 97 int DestReg = MI->getOperand(0).getReg();
113 if (DestReg != SrcReg1) {
115 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
117 if (DestReg != SrcReg2) {
119 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
127 int DestReg = MI->getOperand(0).getReg();
132 if (DestReg != SrcReg1) {
134 TII->get(Hexagon::TFR_cPt), DestReg).
139 TII->get(Hexagon::TFRI_cNotPt), DestReg).
144 TII->get(Hexagon::TFRI_cNotPt_f), DestReg)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 43 unsigned DestReg, unsigned SrcReg,
45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
81 unsigned DestReg, int FI,
85 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
86 isARMLowRegister(DestReg))) && "Unknown regclass!");
89 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
90 isARMLowRegister(DestReg))) {
101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
| Thumb1InstrInfo.h | 44 unsigned DestReg, unsigned SrcReg,
54 unsigned DestReg, int FrameIndex,
|
| Thumb2RegisterInfo.h | 35 unsigned DestReg, unsigned SubIdx, int Val,
|
| Thumb2InstrInfo.h | 45 unsigned DestReg, unsigned SrcReg,
56 unsigned DestReg, int FrameIndex,
|
| Thumb2RegisterInfo.cpp | 37 unsigned DestReg, unsigned SubIdx,
49 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| Thumb2InstrInfo.cpp | 115 unsigned DestReg, unsigned SrcReg,
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
119 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
170 unsigned DestReg, int FI,
186 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
204 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
[all...] |
| Thumb1RegisterInfo.cpp | 67 unsigned DestReg, unsigned SubIdx,
79 .addReg(DestReg, getDefRegState(true), SubIdx)
86 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
93 unsigned DestReg, unsigned BaseReg,
99 bool isHigh = !isARMLowRegister(DestReg) ||
110 unsigned LdReg = DestReg;
111 if (DestReg == ARM::SP) {
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
134 if (DestReg == ARM::SP || isSub)
166 /// a destreg = basereg + immediate in Thumb code
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 37 unsigned DestReg, unsigned SrcReg,
43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
72 if (AMDGPU::M0 == DestReg) {
92 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
94 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
98 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
100 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
104 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
109 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
114 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
[all...] |
| R600MachineScheduler.cpp | 304 unsigned DestReg = MI->getOperand(0).getReg();
305 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
306 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
308 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
310 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
312 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
314 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
385 unsigned DestReg = MI->getOperand(DstIndex).getReg();
392 MO.getReg() == DestReg)
395 // Constrains the regclass of DestReg to assign it to Slo
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 48 * unsigned DestReg, int FrameIndex,
54 unsigned DestReg, unsigned SrcReg, bool KillSrc) const;
56 unsigned &DestReg) const;
|
| NVPTXInstrInfo.cpp | 34 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
36 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
43 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
49 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
52 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
55 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
58 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
66 unsigned &DestReg) const {
81 DestReg = dest.getReg()
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
|
| SIInstrInfo.h | 35 unsigned DestReg, unsigned SrcReg,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
|
| SIInstrInfo.h | 35 unsigned DestReg, unsigned SrcReg,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 56 unsigned DestReg, unsigned SrcReg,
67 unsigned DestReg, int FrameIdx,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 79 unsigned DestReg, unsigned SrcReg,
90 unsigned DestReg, int FrameIndex,
|
| SparcInstrInfo.cpp | 274 unsigned DestReg, unsigned SrcReg,
276 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
277 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
279 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
280 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
282 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
284 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
292 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
299 MovMI->addRegisterDefined(DestReg, TRI);
342 unsigned DestReg, int FI
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 66 unsigned DestReg, unsigned SrcReg,
77 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/CodeGen/ |
| StrongPHIElimination.cpp | 243 unsigned DestReg = BBI->getOperand(0).getReg();
244 addReg(DestReg);
251 unionRegs(DestReg, SrcReg);
287 unsigned DestReg = BBI->getOperand(0).getReg();
288 addReg(DestReg);
293 unionRegs(DestReg, SrcReg);
317 unsigned DestReg = PHI->getOperand(0).getReg();
318 if (!InsertedDestCopies.count(DestReg))
319 MergeLIsAndRename(DestReg, NewReg);
340 unsigned DestReg = I->first
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 469 unsigned DestReg,
525 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
532 unsigned DestReg, unsigned SrcReg,
535 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
537 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
539 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
541 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
543 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
545 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
552 BuildMI(MBB, I, DL, MCID, DestReg)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.h | 95 unsigned DestReg, int FrameIndex,
98 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
110 unsigned DestReg, int FrameIndex,
|
| MipsSEInstrInfo.cpp | 93 unsigned DestReg, unsigned SrcReg,
97 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
113 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
119 if (Mips::CCRRegClass.contains(DestReg))
121 else if (Mips::FGR32RegClass.contains(DestReg))
123 else if (Mips::HIRegsRegClass.contains(DestReg))
124 Opc = Mips::MTHI, DestReg = 0;
125 else if (Mips::LORegsRegClass.contains(DestReg))
126 Opc = Mips::MTLO, DestReg = 0;
127 else if (Mips::HIRegsDSPRegClass.contains(DestReg))
[all...] |
