| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCPredicates.cpp | 1 //===-- PPCPredicates.cpp - PPC Branch Predicate Information --------------===//
19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
21 case PPC::PRED_EQ: return PPC::PRED_NE;
22 case PPC::PRED_NE: return PPC::PRED_EQ;
23 case PPC::PRED_LT: return PPC::PRED_GE
[all...] |
| PPCFixupKinds.h | 1 //===-- PPCFixupKinds.h - PPC Specific Fixup Entries ------------*- C++ -*-===//
15 #undef PPC
18 namespace PPC {
|
| PPCPredicates.h | 1 //===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===//
17 // GCC #defines PPC on Linux but we use it as our namespace name
18 #undef PPC
20 // Generated files will use "namespace PPC". To avoid symbol clash,
21 // undefine PPC here. PPC may be predefined on some hosts.
22 #undef PPC
25 namespace PPC {
|
| PPCAsmBackend.cpp | 1 //===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===//
33 case PPC::fixup_ppc_nofixup:
35 case PPC::fixup_ppc_brcond14:
36 case PPC::fixup_ppc_brcond14abs:
38 case PPC::fixup_ppc_br24:
39 case PPC::fixup_ppc_br24abs:
41 case PPC::fixup_ppc_half16:
43 case PPC::fixup_ppc_half16ds:
55 case PPC::fixup_ppc_half16:
56 case PPC::fixup_ppc_half16ds
[all...] |
| PPCMCCodeEmitter.cpp | 1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
84 if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
85 Opcode == PPC::BL8_NOP_TLS)
117 (MCFixupKind)PPC::fixup_ppc_br24));
128 (MCFixupKind)PPC::fixup_ppc_brcond14));
140 (MCFixupKind)PPC::fixup_ppc_br24abs));
152 (MCFixupKind)PPC::fixup_ppc_brcond14abs));
163 (MCFixupKind)PPC::fixup_ppc_half16));
180 (MCFixupKind)PPC::fixup_ppc_half16))
[all...] |
| PPCMCTargetDesc.h | 17 // GCC #defines PPC on Linux but we use it as our namespace name
18 #undef PPC
45 /// createPPCELFObjectWriter - Construct an PPC ELF object writer.
51 // Generated files will use "namespace PPC". To avoid symbol clash,
52 // undefine PPC here. PPC may be predefined on some hosts.
53 #undef PPC
|
| PPCELFObjectWriter.cpp | 1 //===-- PPCELFObjectWriter.cpp - PPC ELF Writer ---------------------------===//
65 case PPC::fixup_ppc_br24:
66 case PPC::fixup_ppc_br24abs:
69 case PPC::fixup_ppc_brcond14:
70 case PPC::fixup_ppc_brcond14abs:
73 case PPC::fixup_ppc_half16:
102 case PPC::fixup_ppc_br24abs:
105 case PPC::fixup_ppc_brcond14abs:
108 case PPC::fixup_ppc_half16:
265 case PPC::fixup_ppc_half16ds
[all...] |
| PPCMCTargetDesc.cpp | 48 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
74 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRelocations.h | 1 //===-- PPCRelocations.h - PPC Code Relocations -----------------*- C++ -*-===//
19 // Hack to rid us of a PPC pre-processor symbol which is erroneously
20 // defined in a PowerPC header file (bug in Linux/PPC)
21 #ifdef PPC
22 #undef PPC
26 namespace PPC {
|
| PPCFrameLowering.h | 16 #include "PPC.h"
148 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
151 static const SpillSlot darwinOffsets = {PPC::R31, -4};
167 {PPC::F31, -8},
168 {PPC::F30, -16},
169 {PPC::F29, -24},
170 {PPC::F28, -32},
171 {PPC::F27, -40},
172 {PPC::F26, -48},
173 {PPC::F25, -56}
[all...] |
| PPCInstrInfo.cpp | 16 #include "PPC.h"
42 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
45 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
49 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
58 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
59 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
75 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &
[all...] |
| PPCFrameLowering.cpp | 1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
32 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7
[all...] |
| PPCRegisterInfo.cpp | 17 #include "PPC.h"
52 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
56 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
64 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
65 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX
[all...] |
| PPCBranchSelector.cpp | 18 #define DEBUG_TYPE "ppc-branch-select"
19 #include "PPC.h"
54 INITIALIZE_PASS(PPCBSel, "ppc-branch-select", "PowerPC Branch Selector",
116 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
118 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ ||
119 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) &&
158 if (I->getOpcode() == PPC::BCC) {
160 // 0. PPC branch predicat
[all...] |
| PPCISelDAGToDAG.cpp | 1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
11 // converting from a legalized dag to a PPC dag.
15 #define DEBUG_TYPE "ppc-codegen"
16 #include "PPC.h"
43 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
199 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
218 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
219 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
229 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE)
[all...] |
| PPCFastISel.cpp | 17 #include "PPC.h"
136 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocCPT),
138 .addConstantPoolIndex(Idx).addReg(PPC::X2).addMemOperand(MMO);
141 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
142 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA),
144 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
162 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
166 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg
[all...] |
| PPCAsmPrinter.cpp | 20 #include "PPC.h"
98 return "Linux PPC Assembly Printer";
116 return "Darwin PPC Assembly Printer";
249 break; // PPC never has a prefix.
333 case PPC::MovePCtoLR:
334 case PPC::MovePCtoLR8: {
342 OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL)
351 case PPC::LDtocJTI:
352 case PPC::LDtocCPT:
353 case PPC::LDtoc:
[all...] |
| PPCCodeEmitter.cpp | 15 #include "PPC.h"
90 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
131 case PPC::MovePCtoLR:
132 case PPC::MovePCtoLR8:
145 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
146 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
147 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7))
[all...] |
| Makefile | 12 TARGET = PPC
|
| PPCISelLowering.cpp | 1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass)
[all...] |
| PPCSubtarget.cpp | 1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
15 #include "PPC.h"
71 DarwinDirective = PPC::DIR_NONE;
178 CriticalPathRCs.push_back(&PPC::G8RCRegClass);
180 CriticalPathRCs.push_back(&PPC::GPRCRegClass);
182 CriticalPathRCs.push_back(&PPC::F8RCRegClass);
183 CriticalPathRCs.push_back(&PPC::VRRCRegClass);
|
| PPCJITInfo.cpp | 146 // ELF PPC 32 support
418 switch ((PPC::RelocationType)MR->getRelocationType()) {
420 case PPC::reloc_pcrel_bx:
427 case PPC::reloc_pcrel_bcx:
435 case PPC::reloc_absolute_high: // high bits of ref -> low 16 of instr
436 case PPC::reloc_absolute_low: { // low bits of ref -> low 16 of instr
440 if (MR->getRelocationType() == PPC::reloc_absolute_high) {
455 case PPC::reloc_absolute_low_ix: { // low bits of ref -> low 14 of instr
|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
10 // This class prints an PPC MCInst to a .s file.
33 if (MI->getOpcode() == PPC::RLWINM) {
56 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
66 if (MI->getOpcode() == PPC::RLDICR) {
92 switch ((PPC::Predicate)Code) {
93 case PPC::PRED_LT_MINUS:
94 case PPC::PRED_LT_PLUS:
95 case PPC::PRED_LT
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 35 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
36 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
37 PPC::R8, PPC::R9, PPC::R10, PPC::R11
[all...] |
| /external/libpcap/ |
| atmuni31.h | 38 #define PPC 0x05 /* Point-to-point signal msg */
|
