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      1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "MCTargetDesc/PPCMCTargetDesc.h"
     11 #include "MCTargetDesc/PPCMCExpr.h"
     12 #include "llvm/MC/MCTargetAsmParser.h"
     13 #include "llvm/MC/MCStreamer.h"
     14 #include "llvm/MC/MCExpr.h"
     15 #include "llvm/MC/MCInst.h"
     16 #include "llvm/MC/MCRegisterInfo.h"
     17 #include "llvm/MC/MCSubtargetInfo.h"
     18 #include "llvm/MC/MCParser/MCAsmLexer.h"
     19 #include "llvm/MC/MCParser/MCAsmParser.h"
     20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
     21 #include "llvm/ADT/STLExtras.h"
     22 #include "llvm/ADT/SmallString.h"
     23 #include "llvm/ADT/SmallVector.h"
     24 #include "llvm/ADT/StringSwitch.h"
     25 #include "llvm/ADT/Twine.h"
     26 #include "llvm/Support/SourceMgr.h"
     27 #include "llvm/Support/TargetRegistry.h"
     28 #include "llvm/Support/raw_ostream.h"
     29 
     30 using namespace llvm;
     31 
     32 namespace {
     33 
     34 static unsigned RRegs[32] = {
     35   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
     36   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
     37   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
     38   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
     39   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
     40   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
     41   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
     42   PPC::R28, PPC::R29, PPC::R30, PPC::R31
     43 };
     44 static unsigned RRegsNoR0[32] = {
     45   PPC::ZERO,
     46             PPC::R1,  PPC::R2,  PPC::R3,
     47   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
     48   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
     49   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
     50   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
     51   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
     52   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
     53   PPC::R28, PPC::R29, PPC::R30, PPC::R31
     54 };
     55 static unsigned XRegs[32] = {
     56   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
     57   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
     58   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
     59   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
     60   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
     61   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
     62   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
     63   PPC::X28, PPC::X29, PPC::X30, PPC::X31
     64 };
     65 static unsigned XRegsNoX0[32] = {
     66   PPC::ZERO8,
     67             PPC::X1,  PPC::X2,  PPC::X3,
     68   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
     69   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
     70   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
     71   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
     72   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
     73   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
     74   PPC::X28, PPC::X29, PPC::X30, PPC::X31
     75 };
     76 static unsigned FRegs[32] = {
     77   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
     78   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
     79   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
     80   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
     81   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
     82   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
     83   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
     84   PPC::F28, PPC::F29, PPC::F30, PPC::F31
     85 };
     86 static unsigned VRegs[32] = {
     87   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
     88   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
     89   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
     90   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
     91   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
     92   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
     93   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
     94   PPC::V28, PPC::V29, PPC::V30, PPC::V31
     95 };
     96 static unsigned CRBITRegs[32] = {
     97   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
     98   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
     99   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
    100   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
    101   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
    102   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
    103   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
    104   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
    105 };
    106 static unsigned CRRegs[8] = {
    107   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
    108   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
    109 };
    110 
    111 // Evaluate an expression containing condition register
    112 // or condition register field symbols.  Returns positive
    113 // value on success, or -1 on error.
    114 static int64_t
    115 EvaluateCRExpr(const MCExpr *E) {
    116   switch (E->getKind()) {
    117   case MCExpr::Target:
    118     return -1;
    119 
    120   case MCExpr::Constant: {
    121     int64_t Res = cast<MCConstantExpr>(E)->getValue();
    122     return Res < 0 ? -1 : Res;
    123   }
    124 
    125   case MCExpr::SymbolRef: {
    126     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
    127     StringRef Name = SRE->getSymbol().getName();
    128 
    129     if (Name == "lt") return 0;
    130     if (Name == "gt") return 1;
    131     if (Name == "eq") return 2;
    132     if (Name == "so") return 3;
    133     if (Name == "un") return 3;
    134 
    135     if (Name == "cr0") return 0;
    136     if (Name == "cr1") return 1;
    137     if (Name == "cr2") return 2;
    138     if (Name == "cr3") return 3;
    139     if (Name == "cr4") return 4;
    140     if (Name == "cr5") return 5;
    141     if (Name == "cr6") return 6;
    142     if (Name == "cr7") return 7;
    143 
    144     return -1;
    145   }
    146 
    147   case MCExpr::Unary:
    148     return -1;
    149 
    150   case MCExpr::Binary: {
    151     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
    152     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
    153     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
    154     int64_t Res;
    155 
    156     if (LHSVal < 0 || RHSVal < 0)
    157       return -1;
    158 
    159     switch (BE->getOpcode()) {
    160     default: return -1;
    161     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
    162     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
    163     }
    164 
    165     return Res < 0 ? -1 : Res;
    166   }
    167   }
    168 
    169   llvm_unreachable("Invalid expression kind!");
    170 }
    171 
    172 struct PPCOperand;
    173 
    174 class PPCAsmParser : public MCTargetAsmParser {
    175   MCSubtargetInfo &STI;
    176   MCAsmParser &Parser;
    177   bool IsPPC64;
    178 
    179   MCAsmParser &getParser() const { return Parser; }
    180   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
    181 
    182   void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
    183   bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
    184 
    185   bool isPPC64() const { return IsPPC64; }
    186 
    187   bool MatchRegisterName(const AsmToken &Tok,
    188                          unsigned &RegNo, int64_t &IntVal);
    189 
    190   virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
    191 
    192   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
    193                                         PPCMCExpr::VariantKind &Variant);
    194   const MCExpr *FixupVariantKind(const MCExpr *E);
    195   bool ParseExpression(const MCExpr *&EVal);
    196 
    197   bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
    198 
    199   bool ParseDirectiveWord(unsigned Size, SMLoc L);
    200   bool ParseDirectiveTC(unsigned Size, SMLoc L);
    201   bool ParseDirectiveMachine(SMLoc L);
    202 
    203   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
    204                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
    205                                MCStreamer &Out, unsigned &ErrorInfo,
    206                                bool MatchingInlineAsm);
    207 
    208   void ProcessInstruction(MCInst &Inst,
    209                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
    210 
    211   /// @name Auto-generated Match Functions
    212   /// {
    213 
    214 #define GET_ASSEMBLER_HEADER
    215 #include "PPCGenAsmMatcher.inc"
    216 
    217   /// }
    218 
    219 
    220 public:
    221   PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
    222     : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
    223     // Check for 64-bit vs. 32-bit pointer mode.
    224     Triple TheTriple(STI.getTargetTriple());
    225     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
    226                TheTriple.getArch() == Triple::ppc64le);
    227     // Initialize the set of available features.
    228     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
    229   }
    230 
    231   virtual bool ParseInstruction(ParseInstructionInfo &Info,
    232                                 StringRef Name, SMLoc NameLoc,
    233                                 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
    234 
    235   virtual bool ParseDirective(AsmToken DirectiveID);
    236 
    237   unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
    238 };
    239 
    240 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
    241 /// instruction.
    242 struct PPCOperand : public MCParsedAsmOperand {
    243   enum KindTy {
    244     Token,
    245     Immediate,
    246     Expression,
    247     TLSRegister
    248   } Kind;
    249 
    250   SMLoc StartLoc, EndLoc;
    251   bool IsPPC64;
    252 
    253   struct TokOp {
    254     const char *Data;
    255     unsigned Length;
    256   };
    257 
    258   struct ImmOp {
    259     int64_t Val;
    260   };
    261 
    262   struct ExprOp {
    263     const MCExpr *Val;
    264     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
    265   };
    266 
    267   struct TLSRegOp {
    268     const MCSymbolRefExpr *Sym;
    269   };
    270 
    271   union {
    272     struct TokOp Tok;
    273     struct ImmOp Imm;
    274     struct ExprOp Expr;
    275     struct TLSRegOp TLSReg;
    276   };
    277 
    278   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
    279 public:
    280   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
    281     Kind = o.Kind;
    282     StartLoc = o.StartLoc;
    283     EndLoc = o.EndLoc;
    284     IsPPC64 = o.IsPPC64;
    285     switch (Kind) {
    286     case Token:
    287       Tok = o.Tok;
    288       break;
    289     case Immediate:
    290       Imm = o.Imm;
    291       break;
    292     case Expression:
    293       Expr = o.Expr;
    294       break;
    295     case TLSRegister:
    296       TLSReg = o.TLSReg;
    297       break;
    298     }
    299   }
    300 
    301   /// getStartLoc - Get the location of the first token of this operand.
    302   SMLoc getStartLoc() const { return StartLoc; }
    303 
    304   /// getEndLoc - Get the location of the last token of this operand.
    305   SMLoc getEndLoc() const { return EndLoc; }
    306 
    307   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
    308   bool isPPC64() const { return IsPPC64; }
    309 
    310   int64_t getImm() const {
    311     assert(Kind == Immediate && "Invalid access!");
    312     return Imm.Val;
    313   }
    314 
    315   const MCExpr *getExpr() const {
    316     assert(Kind == Expression && "Invalid access!");
    317     return Expr.Val;
    318   }
    319 
    320   int64_t getExprCRVal() const {
    321     assert(Kind == Expression && "Invalid access!");
    322     return Expr.CRVal;
    323   }
    324 
    325   const MCExpr *getTLSReg() const {
    326     assert(Kind == TLSRegister && "Invalid access!");
    327     return TLSReg.Sym;
    328   }
    329 
    330   unsigned getReg() const {
    331     assert(isRegNumber() && "Invalid access!");
    332     return (unsigned) Imm.Val;
    333   }
    334 
    335   unsigned getCCReg() const {
    336     assert(isCCRegNumber() && "Invalid access!");
    337     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
    338   }
    339 
    340   unsigned getCRBit() const {
    341     assert(isCRBitNumber() && "Invalid access!");
    342     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
    343   }
    344 
    345   unsigned getCRBitMask() const {
    346     assert(isCRBitMask() && "Invalid access!");
    347     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
    348   }
    349 
    350   bool isToken() const { return Kind == Token; }
    351   bool isImm() const { return Kind == Immediate || Kind == Expression; }
    352   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
    353   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
    354   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
    355   bool isU16Imm() const { return Kind == Expression ||
    356                                  (Kind == Immediate && isUInt<16>(getImm())); }
    357   bool isS16Imm() const { return Kind == Expression ||
    358                                  (Kind == Immediate && isInt<16>(getImm())); }
    359   bool isS16ImmX4() const { return Kind == Expression ||
    360                                    (Kind == Immediate && isInt<16>(getImm()) &&
    361                                     (getImm() & 3) == 0); }
    362   bool isS17Imm() const { return Kind == Expression ||
    363                                  (Kind == Immediate && isInt<17>(getImm())); }
    364   bool isTLSReg() const { return Kind == TLSRegister; }
    365   bool isDirectBr() const { return Kind == Expression ||
    366                                    (Kind == Immediate && isInt<26>(getImm()) &&
    367                                     (getImm() & 3) == 0); }
    368   bool isCondBr() const { return Kind == Expression ||
    369                                  (Kind == Immediate && isInt<16>(getImm()) &&
    370                                   (getImm() & 3) == 0); }
    371   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
    372   bool isCCRegNumber() const { return (Kind == Expression
    373                                        && isUInt<3>(getExprCRVal())) ||
    374                                       (Kind == Immediate
    375                                        && isUInt<3>(getImm())); }
    376   bool isCRBitNumber() const { return (Kind == Expression
    377                                        && isUInt<5>(getExprCRVal())) ||
    378                                       (Kind == Immediate
    379                                        && isUInt<5>(getImm())); }
    380   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
    381                                     isPowerOf2_32(getImm()); }
    382   bool isMem() const { return false; }
    383   bool isReg() const { return false; }
    384 
    385   void addRegOperands(MCInst &Inst, unsigned N) const {
    386     llvm_unreachable("addRegOperands");
    387   }
    388 
    389   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
    390     assert(N == 1 && "Invalid number of operands!");
    391     Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
    392   }
    393 
    394   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
    395     assert(N == 1 && "Invalid number of operands!");
    396     Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
    397   }
    398 
    399   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
    400     assert(N == 1 && "Invalid number of operands!");
    401     Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
    402   }
    403 
    404   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
    405     assert(N == 1 && "Invalid number of operands!");
    406     Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
    407   }
    408 
    409   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
    410     if (isPPC64())
    411       addRegG8RCOperands(Inst, N);
    412     else
    413       addRegGPRCOperands(Inst, N);
    414   }
    415 
    416   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
    417     if (isPPC64())
    418       addRegG8RCNoX0Operands(Inst, N);
    419     else
    420       addRegGPRCNoR0Operands(Inst, N);
    421   }
    422 
    423   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
    424     assert(N == 1 && "Invalid number of operands!");
    425     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
    426   }
    427 
    428   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
    429     assert(N == 1 && "Invalid number of operands!");
    430     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
    431   }
    432 
    433   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
    434     assert(N == 1 && "Invalid number of operands!");
    435     Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
    436   }
    437 
    438   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
    439     assert(N == 1 && "Invalid number of operands!");
    440     Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
    441   }
    442 
    443   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
    444     assert(N == 1 && "Invalid number of operands!");
    445     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
    446   }
    447 
    448   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
    449     assert(N == 1 && "Invalid number of operands!");
    450     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
    451   }
    452 
    453   void addImmOperands(MCInst &Inst, unsigned N) const {
    454     assert(N == 1 && "Invalid number of operands!");
    455     if (Kind == Immediate)
    456       Inst.addOperand(MCOperand::CreateImm(getImm()));
    457     else
    458       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
    459   }
    460 
    461   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
    462     assert(N == 1 && "Invalid number of operands!");
    463     if (Kind == Immediate)
    464       Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
    465     else
    466       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
    467   }
    468 
    469   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
    470     assert(N == 1 && "Invalid number of operands!");
    471     Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
    472   }
    473 
    474   StringRef getToken() const {
    475     assert(Kind == Token && "Invalid access!");
    476     return StringRef(Tok.Data, Tok.Length);
    477   }
    478 
    479   virtual void print(raw_ostream &OS) const;
    480 
    481   static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
    482     PPCOperand *Op = new PPCOperand(Token);
    483     Op->Tok.Data = Str.data();
    484     Op->Tok.Length = Str.size();
    485     Op->StartLoc = S;
    486     Op->EndLoc = S;
    487     Op->IsPPC64 = IsPPC64;
    488     return Op;
    489   }
    490 
    491   static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
    492                                                bool IsPPC64) {
    493     // Allocate extra memory for the string and copy it.
    494     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
    495     PPCOperand *Op = new (Mem) PPCOperand(Token);
    496     Op->Tok.Data = (const char *)(Op + 1);
    497     Op->Tok.Length = Str.size();
    498     std::memcpy((char *)(Op + 1), Str.data(), Str.size());
    499     Op->StartLoc = S;
    500     Op->EndLoc = S;
    501     Op->IsPPC64 = IsPPC64;
    502     return Op;
    503   }
    504 
    505   static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
    506     PPCOperand *Op = new PPCOperand(Immediate);
    507     Op->Imm.Val = Val;
    508     Op->StartLoc = S;
    509     Op->EndLoc = E;
    510     Op->IsPPC64 = IsPPC64;
    511     return Op;
    512   }
    513 
    514   static PPCOperand *CreateExpr(const MCExpr *Val,
    515                                 SMLoc S, SMLoc E, bool IsPPC64) {
    516     PPCOperand *Op = new PPCOperand(Expression);
    517     Op->Expr.Val = Val;
    518     Op->Expr.CRVal = EvaluateCRExpr(Val);
    519     Op->StartLoc = S;
    520     Op->EndLoc = E;
    521     Op->IsPPC64 = IsPPC64;
    522     return Op;
    523   }
    524 
    525   static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
    526                                   SMLoc S, SMLoc E, bool IsPPC64) {
    527     PPCOperand *Op = new PPCOperand(TLSRegister);
    528     Op->TLSReg.Sym = Sym;
    529     Op->StartLoc = S;
    530     Op->EndLoc = E;
    531     Op->IsPPC64 = IsPPC64;
    532     return Op;
    533   }
    534 
    535   static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
    536                                       SMLoc S, SMLoc E, bool IsPPC64) {
    537     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
    538       return CreateImm(CE->getValue(), S, E, IsPPC64);
    539 
    540     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
    541       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
    542         return CreateTLSReg(SRE, S, E, IsPPC64);
    543 
    544     return CreateExpr(Val, S, E, IsPPC64);
    545   }
    546 };
    547 
    548 } // end anonymous namespace.
    549 
    550 void PPCOperand::print(raw_ostream &OS) const {
    551   switch (Kind) {
    552   case Token:
    553     OS << "'" << getToken() << "'";
    554     break;
    555   case Immediate:
    556     OS << getImm();
    557     break;
    558   case Expression:
    559     getExpr()->print(OS);
    560     break;
    561   case TLSRegister:
    562     getTLSReg()->print(OS);
    563     break;
    564   }
    565 }
    566 
    567 
    568 void PPCAsmParser::
    569 ProcessInstruction(MCInst &Inst,
    570                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
    571   int Opcode = Inst.getOpcode();
    572   switch (Opcode) {
    573   case PPC::LAx: {
    574     MCInst TmpInst;
    575     TmpInst.setOpcode(PPC::LA);
    576     TmpInst.addOperand(Inst.getOperand(0));
    577     TmpInst.addOperand(Inst.getOperand(2));
    578     TmpInst.addOperand(Inst.getOperand(1));
    579     Inst = TmpInst;
    580     break;
    581   }
    582   case PPC::SUBI: {
    583     MCInst TmpInst;
    584     int64_t N = Inst.getOperand(2).getImm();
    585     TmpInst.setOpcode(PPC::ADDI);
    586     TmpInst.addOperand(Inst.getOperand(0));
    587     TmpInst.addOperand(Inst.getOperand(1));
    588     TmpInst.addOperand(MCOperand::CreateImm(-N));
    589     Inst = TmpInst;
    590     break;
    591   }
    592   case PPC::SUBIS: {
    593     MCInst TmpInst;
    594     int64_t N = Inst.getOperand(2).getImm();
    595     TmpInst.setOpcode(PPC::ADDIS);
    596     TmpInst.addOperand(Inst.getOperand(0));
    597     TmpInst.addOperand(Inst.getOperand(1));
    598     TmpInst.addOperand(MCOperand::CreateImm(-N));
    599     Inst = TmpInst;
    600     break;
    601   }
    602   case PPC::SUBIC: {
    603     MCInst TmpInst;
    604     int64_t N = Inst.getOperand(2).getImm();
    605     TmpInst.setOpcode(PPC::ADDIC);
    606     TmpInst.addOperand(Inst.getOperand(0));
    607     TmpInst.addOperand(Inst.getOperand(1));
    608     TmpInst.addOperand(MCOperand::CreateImm(-N));
    609     Inst = TmpInst;
    610     break;
    611   }
    612   case PPC::SUBICo: {
    613     MCInst TmpInst;
    614     int64_t N = Inst.getOperand(2).getImm();
    615     TmpInst.setOpcode(PPC::ADDICo);
    616     TmpInst.addOperand(Inst.getOperand(0));
    617     TmpInst.addOperand(Inst.getOperand(1));
    618     TmpInst.addOperand(MCOperand::CreateImm(-N));
    619     Inst = TmpInst;
    620     break;
    621   }
    622   case PPC::EXTLWI:
    623   case PPC::EXTLWIo: {
    624     MCInst TmpInst;
    625     int64_t N = Inst.getOperand(2).getImm();
    626     int64_t B = Inst.getOperand(3).getImm();
    627     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
    628     TmpInst.addOperand(Inst.getOperand(0));
    629     TmpInst.addOperand(Inst.getOperand(1));
    630     TmpInst.addOperand(MCOperand::CreateImm(B));
    631     TmpInst.addOperand(MCOperand::CreateImm(0));
    632     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
    633     Inst = TmpInst;
    634     break;
    635   }
    636   case PPC::EXTRWI:
    637   case PPC::EXTRWIo: {
    638     MCInst TmpInst;
    639     int64_t N = Inst.getOperand(2).getImm();
    640     int64_t B = Inst.getOperand(3).getImm();
    641     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
    642     TmpInst.addOperand(Inst.getOperand(0));
    643     TmpInst.addOperand(Inst.getOperand(1));
    644     TmpInst.addOperand(MCOperand::CreateImm(B + N));
    645     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
    646     TmpInst.addOperand(MCOperand::CreateImm(31));
    647     Inst = TmpInst;
    648     break;
    649   }
    650   case PPC::INSLWI:
    651   case PPC::INSLWIo: {
    652     MCInst TmpInst;
    653     int64_t N = Inst.getOperand(2).getImm();
    654     int64_t B = Inst.getOperand(3).getImm();
    655     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
    656     TmpInst.addOperand(Inst.getOperand(0));
    657     TmpInst.addOperand(Inst.getOperand(0));
    658     TmpInst.addOperand(Inst.getOperand(1));
    659     TmpInst.addOperand(MCOperand::CreateImm(32 - B));
    660     TmpInst.addOperand(MCOperand::CreateImm(B));
    661     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
    662     Inst = TmpInst;
    663     break;
    664   }
    665   case PPC::INSRWI:
    666   case PPC::INSRWIo: {
    667     MCInst TmpInst;
    668     int64_t N = Inst.getOperand(2).getImm();
    669     int64_t B = Inst.getOperand(3).getImm();
    670     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
    671     TmpInst.addOperand(Inst.getOperand(0));
    672     TmpInst.addOperand(Inst.getOperand(0));
    673     TmpInst.addOperand(Inst.getOperand(1));
    674     TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
    675     TmpInst.addOperand(MCOperand::CreateImm(B));
    676     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
    677     Inst = TmpInst;
    678     break;
    679   }
    680   case PPC::ROTRWI:
    681   case PPC::ROTRWIo: {
    682     MCInst TmpInst;
    683     int64_t N = Inst.getOperand(2).getImm();
    684     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
    685     TmpInst.addOperand(Inst.getOperand(0));
    686     TmpInst.addOperand(Inst.getOperand(1));
    687     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
    688     TmpInst.addOperand(MCOperand::CreateImm(0));
    689     TmpInst.addOperand(MCOperand::CreateImm(31));
    690     Inst = TmpInst;
    691     break;
    692   }
    693   case PPC::SLWI:
    694   case PPC::SLWIo: {
    695     MCInst TmpInst;
    696     int64_t N = Inst.getOperand(2).getImm();
    697     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
    698     TmpInst.addOperand(Inst.getOperand(0));
    699     TmpInst.addOperand(Inst.getOperand(1));
    700     TmpInst.addOperand(MCOperand::CreateImm(N));
    701     TmpInst.addOperand(MCOperand::CreateImm(0));
    702     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
    703     Inst = TmpInst;
    704     break;
    705   }
    706   case PPC::SRWI:
    707   case PPC::SRWIo: {
    708     MCInst TmpInst;
    709     int64_t N = Inst.getOperand(2).getImm();
    710     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
    711     TmpInst.addOperand(Inst.getOperand(0));
    712     TmpInst.addOperand(Inst.getOperand(1));
    713     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
    714     TmpInst.addOperand(MCOperand::CreateImm(N));
    715     TmpInst.addOperand(MCOperand::CreateImm(31));
    716     Inst = TmpInst;
    717     break;
    718   }
    719   case PPC::CLRRWI:
    720   case PPC::CLRRWIo: {
    721     MCInst TmpInst;
    722     int64_t N = Inst.getOperand(2).getImm();
    723     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
    724     TmpInst.addOperand(Inst.getOperand(0));
    725     TmpInst.addOperand(Inst.getOperand(1));
    726     TmpInst.addOperand(MCOperand::CreateImm(0));
    727     TmpInst.addOperand(MCOperand::CreateImm(0));
    728     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
    729     Inst = TmpInst;
    730     break;
    731   }
    732   case PPC::CLRLSLWI:
    733   case PPC::CLRLSLWIo: {
    734     MCInst TmpInst;
    735     int64_t B = Inst.getOperand(2).getImm();
    736     int64_t N = Inst.getOperand(3).getImm();
    737     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
    738     TmpInst.addOperand(Inst.getOperand(0));
    739     TmpInst.addOperand(Inst.getOperand(1));
    740     TmpInst.addOperand(MCOperand::CreateImm(N));
    741     TmpInst.addOperand(MCOperand::CreateImm(B - N));
    742     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
    743     Inst = TmpInst;
    744     break;
    745   }
    746   case PPC::EXTLDI:
    747   case PPC::EXTLDIo: {
    748     MCInst TmpInst;
    749     int64_t N = Inst.getOperand(2).getImm();
    750     int64_t B = Inst.getOperand(3).getImm();
    751     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
    752     TmpInst.addOperand(Inst.getOperand(0));
    753     TmpInst.addOperand(Inst.getOperand(1));
    754     TmpInst.addOperand(MCOperand::CreateImm(B));
    755     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
    756     Inst = TmpInst;
    757     break;
    758   }
    759   case PPC::EXTRDI:
    760   case PPC::EXTRDIo: {
    761     MCInst TmpInst;
    762     int64_t N = Inst.getOperand(2).getImm();
    763     int64_t B = Inst.getOperand(3).getImm();
    764     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
    765     TmpInst.addOperand(Inst.getOperand(0));
    766     TmpInst.addOperand(Inst.getOperand(1));
    767     TmpInst.addOperand(MCOperand::CreateImm(B + N));
    768     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
    769     Inst = TmpInst;
    770     break;
    771   }
    772   case PPC::INSRDI:
    773   case PPC::INSRDIo: {
    774     MCInst TmpInst;
    775     int64_t N = Inst.getOperand(2).getImm();
    776     int64_t B = Inst.getOperand(3).getImm();
    777     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
    778     TmpInst.addOperand(Inst.getOperand(0));
    779     TmpInst.addOperand(Inst.getOperand(0));
    780     TmpInst.addOperand(Inst.getOperand(1));
    781     TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
    782     TmpInst.addOperand(MCOperand::CreateImm(B));
    783     Inst = TmpInst;
    784     break;
    785   }
    786   case PPC::ROTRDI:
    787   case PPC::ROTRDIo: {
    788     MCInst TmpInst;
    789     int64_t N = Inst.getOperand(2).getImm();
    790     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
    791     TmpInst.addOperand(Inst.getOperand(0));
    792     TmpInst.addOperand(Inst.getOperand(1));
    793     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
    794     TmpInst.addOperand(MCOperand::CreateImm(0));
    795     Inst = TmpInst;
    796     break;
    797   }
    798   case PPC::SLDI:
    799   case PPC::SLDIo: {
    800     MCInst TmpInst;
    801     int64_t N = Inst.getOperand(2).getImm();
    802     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
    803     TmpInst.addOperand(Inst.getOperand(0));
    804     TmpInst.addOperand(Inst.getOperand(1));
    805     TmpInst.addOperand(MCOperand::CreateImm(N));
    806     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
    807     Inst = TmpInst;
    808     break;
    809   }
    810   case PPC::SRDI:
    811   case PPC::SRDIo: {
    812     MCInst TmpInst;
    813     int64_t N = Inst.getOperand(2).getImm();
    814     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
    815     TmpInst.addOperand(Inst.getOperand(0));
    816     TmpInst.addOperand(Inst.getOperand(1));
    817     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
    818     TmpInst.addOperand(MCOperand::CreateImm(N));
    819     Inst = TmpInst;
    820     break;
    821   }
    822   case PPC::CLRRDI:
    823   case PPC::CLRRDIo: {
    824     MCInst TmpInst;
    825     int64_t N = Inst.getOperand(2).getImm();
    826     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
    827     TmpInst.addOperand(Inst.getOperand(0));
    828     TmpInst.addOperand(Inst.getOperand(1));
    829     TmpInst.addOperand(MCOperand::CreateImm(0));
    830     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
    831     Inst = TmpInst;
    832     break;
    833   }
    834   case PPC::CLRLSLDI:
    835   case PPC::CLRLSLDIo: {
    836     MCInst TmpInst;
    837     int64_t B = Inst.getOperand(2).getImm();
    838     int64_t N = Inst.getOperand(3).getImm();
    839     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
    840     TmpInst.addOperand(Inst.getOperand(0));
    841     TmpInst.addOperand(Inst.getOperand(1));
    842     TmpInst.addOperand(MCOperand::CreateImm(N));
    843     TmpInst.addOperand(MCOperand::CreateImm(B - N));
    844     Inst = TmpInst;
    845     break;
    846   }
    847   }
    848 }
    849 
    850 bool PPCAsmParser::
    851 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
    852                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
    853                         MCStreamer &Out, unsigned &ErrorInfo,
    854                         bool MatchingInlineAsm) {
    855   MCInst Inst;
    856 
    857   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
    858   default: break;
    859   case Match_Success:
    860     // Post-process instructions (typically extended mnemonics)
    861     ProcessInstruction(Inst, Operands);
    862     Inst.setLoc(IDLoc);
    863     Out.EmitInstruction(Inst);
    864     return false;
    865   case Match_MissingFeature:
    866     return Error(IDLoc, "instruction use requires an option to be enabled");
    867   case Match_MnemonicFail:
    868       return Error(IDLoc, "unrecognized instruction mnemonic");
    869   case Match_InvalidOperand: {
    870     SMLoc ErrorLoc = IDLoc;
    871     if (ErrorInfo != ~0U) {
    872       if (ErrorInfo >= Operands.size())
    873         return Error(IDLoc, "too few operands for instruction");
    874 
    875       ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
    876       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
    877     }
    878 
    879     return Error(ErrorLoc, "invalid operand for instruction");
    880   }
    881   }
    882 
    883   llvm_unreachable("Implement any new match types added!");
    884 }
    885 
    886 bool PPCAsmParser::
    887 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
    888   if (Tok.is(AsmToken::Identifier)) {
    889     StringRef Name = Tok.getString();
    890 
    891     if (Name.equals_lower("lr")) {
    892       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
    893       IntVal = 8;
    894       return false;
    895     } else if (Name.equals_lower("ctr")) {
    896       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
    897       IntVal = 9;
    898       return false;
    899     } else if (Name.equals_lower("vrsave")) {
    900       RegNo = PPC::VRSAVE;
    901       IntVal = 256;
    902       return false;
    903     } else if (Name.substr(0, 1).equals_lower("r") &&
    904                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
    905       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
    906       return false;
    907     } else if (Name.substr(0, 1).equals_lower("f") &&
    908                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
    909       RegNo = FRegs[IntVal];
    910       return false;
    911     } else if (Name.substr(0, 1).equals_lower("v") &&
    912                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
    913       RegNo = VRegs[IntVal];
    914       return false;
    915     } else if (Name.substr(0, 2).equals_lower("cr") &&
    916                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
    917       RegNo = CRRegs[IntVal];
    918       return false;
    919     }
    920   }
    921 
    922   return true;
    923 }
    924 
    925 bool PPCAsmParser::
    926 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
    927   const AsmToken &Tok = Parser.getTok();
    928   StartLoc = Tok.getLoc();
    929   EndLoc = Tok.getEndLoc();
    930   RegNo = 0;
    931   int64_t IntVal;
    932 
    933   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
    934     Parser.Lex(); // Eat identifier token.
    935     return false;
    936   }
    937 
    938   return Error(StartLoc, "invalid register name");
    939 }
    940 
    941 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
    942 /// the expression and check for VK_PPC_LO/HI/HA
    943 /// symbol variants.  If all symbols with modifier use the same
    944 /// variant, return the corresponding PPCMCExpr::VariantKind,
    945 /// and a modified expression using the default symbol variant.
    946 /// Otherwise, return NULL.
    947 const MCExpr *PPCAsmParser::
    948 ExtractModifierFromExpr(const MCExpr *E,
    949                         PPCMCExpr::VariantKind &Variant) {
    950   MCContext &Context = getParser().getContext();
    951   Variant = PPCMCExpr::VK_PPC_None;
    952 
    953   switch (E->getKind()) {
    954   case MCExpr::Target:
    955   case MCExpr::Constant:
    956     return 0;
    957 
    958   case MCExpr::SymbolRef: {
    959     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
    960 
    961     switch (SRE->getKind()) {
    962     case MCSymbolRefExpr::VK_PPC_LO:
    963       Variant = PPCMCExpr::VK_PPC_LO;
    964       break;
    965     case MCSymbolRefExpr::VK_PPC_HI:
    966       Variant = PPCMCExpr::VK_PPC_HI;
    967       break;
    968     case MCSymbolRefExpr::VK_PPC_HA:
    969       Variant = PPCMCExpr::VK_PPC_HA;
    970       break;
    971     case MCSymbolRefExpr::VK_PPC_HIGHER:
    972       Variant = PPCMCExpr::VK_PPC_HIGHER;
    973       break;
    974     case MCSymbolRefExpr::VK_PPC_HIGHERA:
    975       Variant = PPCMCExpr::VK_PPC_HIGHERA;
    976       break;
    977     case MCSymbolRefExpr::VK_PPC_HIGHEST:
    978       Variant = PPCMCExpr::VK_PPC_HIGHEST;
    979       break;
    980     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
    981       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
    982       break;
    983     default:
    984       return 0;
    985     }
    986 
    987     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
    988   }
    989 
    990   case MCExpr::Unary: {
    991     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
    992     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
    993     if (!Sub)
    994       return 0;
    995     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
    996   }
    997 
    998   case MCExpr::Binary: {
    999     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
   1000     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
   1001     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
   1002     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
   1003 
   1004     if (!LHS && !RHS)
   1005       return 0;
   1006 
   1007     if (!LHS) LHS = BE->getLHS();
   1008     if (!RHS) RHS = BE->getRHS();
   1009 
   1010     if (LHSVariant == PPCMCExpr::VK_PPC_None)
   1011       Variant = RHSVariant;
   1012     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
   1013       Variant = LHSVariant;
   1014     else if (LHSVariant == RHSVariant)
   1015       Variant = LHSVariant;
   1016     else
   1017       return 0;
   1018 
   1019     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
   1020   }
   1021   }
   1022 
   1023   llvm_unreachable("Invalid expression kind!");
   1024 }
   1025 
   1026 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
   1027 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
   1028 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
   1029 /// FIXME: This is a hack.
   1030 const MCExpr *PPCAsmParser::
   1031 FixupVariantKind(const MCExpr *E) {
   1032   MCContext &Context = getParser().getContext();
   1033 
   1034   switch (E->getKind()) {
   1035   case MCExpr::Target:
   1036   case MCExpr::Constant:
   1037     return E;
   1038 
   1039   case MCExpr::SymbolRef: {
   1040     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
   1041     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
   1042 
   1043     switch (SRE->getKind()) {
   1044     case MCSymbolRefExpr::VK_TLSGD:
   1045       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
   1046       break;
   1047     case MCSymbolRefExpr::VK_TLSLD:
   1048       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
   1049       break;
   1050     default:
   1051       return E;
   1052     }
   1053     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
   1054   }
   1055 
   1056   case MCExpr::Unary: {
   1057     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
   1058     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
   1059     if (Sub == UE->getSubExpr())
   1060       return E;
   1061     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
   1062   }
   1063 
   1064   case MCExpr::Binary: {
   1065     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
   1066     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
   1067     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
   1068     if (LHS == BE->getLHS() && RHS == BE->getRHS())
   1069       return E;
   1070     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
   1071   }
   1072   }
   1073 
   1074   llvm_unreachable("Invalid expression kind!");
   1075 }
   1076 
   1077 /// Parse an expression.  This differs from the default "parseExpression"
   1078 /// in that it handles complex \code @l/@ha \endcode modifiers.
   1079 bool PPCAsmParser::
   1080 ParseExpression(const MCExpr *&EVal) {
   1081   if (getParser().parseExpression(EVal))
   1082     return true;
   1083 
   1084   EVal = FixupVariantKind(EVal);
   1085 
   1086   PPCMCExpr::VariantKind Variant;
   1087   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
   1088   if (E)
   1089     EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
   1090 
   1091   return false;
   1092 }
   1093 
   1094 bool PPCAsmParser::
   1095 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   1096   SMLoc S = Parser.getTok().getLoc();
   1097   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   1098   const MCExpr *EVal;
   1099   PPCOperand *Op;
   1100 
   1101   // Attempt to parse the next token as an immediate
   1102   switch (getLexer().getKind()) {
   1103   // Special handling for register names.  These are interpreted
   1104   // as immediates corresponding to the register number.
   1105   case AsmToken::Percent:
   1106     Parser.Lex(); // Eat the '%'.
   1107     unsigned RegNo;
   1108     int64_t IntVal;
   1109     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
   1110       Parser.Lex(); // Eat the identifier token.
   1111       Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
   1112       Operands.push_back(Op);
   1113       return false;
   1114     }
   1115     return Error(S, "invalid register name");
   1116 
   1117   // All other expressions
   1118   case AsmToken::LParen:
   1119   case AsmToken::Plus:
   1120   case AsmToken::Minus:
   1121   case AsmToken::Integer:
   1122   case AsmToken::Identifier:
   1123   case AsmToken::Dot:
   1124   case AsmToken::Dollar:
   1125     if (!ParseExpression(EVal))
   1126       break;
   1127     /* fall through */
   1128   default:
   1129     return Error(S, "unknown operand");
   1130   }
   1131 
   1132   // Push the parsed operand into the list of operands
   1133   Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
   1134   Operands.push_back(Op);
   1135 
   1136   // Check whether this is a TLS call expression
   1137   bool TLSCall = false;
   1138   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
   1139     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
   1140 
   1141   if (TLSCall && getLexer().is(AsmToken::LParen)) {
   1142     const MCExpr *TLSSym;
   1143 
   1144     Parser.Lex(); // Eat the '('.
   1145     S = Parser.getTok().getLoc();
   1146     if (ParseExpression(TLSSym))
   1147       return Error(S, "invalid TLS call expression");
   1148     if (getLexer().isNot(AsmToken::RParen))
   1149       return Error(Parser.getTok().getLoc(), "missing ')'");
   1150     E = Parser.getTok().getLoc();
   1151     Parser.Lex(); // Eat the ')'.
   1152 
   1153     Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
   1154     Operands.push_back(Op);
   1155   }
   1156 
   1157   // Otherwise, check for D-form memory operands
   1158   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
   1159     Parser.Lex(); // Eat the '('.
   1160     S = Parser.getTok().getLoc();
   1161 
   1162     int64_t IntVal;
   1163     switch (getLexer().getKind()) {
   1164     case AsmToken::Percent:
   1165       Parser.Lex(); // Eat the '%'.
   1166       unsigned RegNo;
   1167       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
   1168         return Error(S, "invalid register name");
   1169       Parser.Lex(); // Eat the identifier token.
   1170       break;
   1171 
   1172     case AsmToken::Integer:
   1173       if (getParser().parseAbsoluteExpression(IntVal) ||
   1174           IntVal < 0 || IntVal > 31)
   1175         return Error(S, "invalid register number");
   1176       break;
   1177 
   1178     default:
   1179       return Error(S, "invalid memory operand");
   1180     }
   1181 
   1182     if (getLexer().isNot(AsmToken::RParen))
   1183       return Error(Parser.getTok().getLoc(), "missing ')'");
   1184     E = Parser.getTok().getLoc();
   1185     Parser.Lex(); // Eat the ')'.
   1186 
   1187     Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
   1188     Operands.push_back(Op);
   1189   }
   1190 
   1191   return false;
   1192 }
   1193 
   1194 /// Parse an instruction mnemonic followed by its operands.
   1195 bool PPCAsmParser::
   1196 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
   1197                  SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   1198   // The first operand is the token for the instruction name.
   1199   // If the next character is a '+' or '-', we need to add it to the
   1200   // instruction name, to match what TableGen is doing.
   1201   std::string NewOpcode;
   1202   if (getLexer().is(AsmToken::Plus)) {
   1203     getLexer().Lex();
   1204     NewOpcode = Name;
   1205     NewOpcode += '+';
   1206     Name = NewOpcode;
   1207   }
   1208   if (getLexer().is(AsmToken::Minus)) {
   1209     getLexer().Lex();
   1210     NewOpcode = Name;
   1211     NewOpcode += '-';
   1212     Name = NewOpcode;
   1213   }
   1214   // If the instruction ends in a '.', we need to create a separate
   1215   // token for it, to match what TableGen is doing.
   1216   size_t Dot = Name.find('.');
   1217   StringRef Mnemonic = Name.slice(0, Dot);
   1218   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
   1219     Operands.push_back(
   1220         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
   1221   else
   1222     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
   1223   if (Dot != StringRef::npos) {
   1224     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
   1225     StringRef DotStr = Name.slice(Dot, StringRef::npos);
   1226     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
   1227       Operands.push_back(
   1228           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
   1229     else
   1230       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
   1231   }
   1232 
   1233   // If there are no more operands then finish
   1234   if (getLexer().is(AsmToken::EndOfStatement))
   1235     return false;
   1236 
   1237   // Parse the first operand
   1238   if (ParseOperand(Operands))
   1239     return true;
   1240 
   1241   while (getLexer().isNot(AsmToken::EndOfStatement) &&
   1242          getLexer().is(AsmToken::Comma)) {
   1243     // Consume the comma token
   1244     getLexer().Lex();
   1245 
   1246     // Parse the next operand
   1247     if (ParseOperand(Operands))
   1248       return true;
   1249   }
   1250 
   1251   return false;
   1252 }
   1253 
   1254 /// ParseDirective parses the PPC specific directives
   1255 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
   1256   StringRef IDVal = DirectiveID.getIdentifier();
   1257   if (IDVal == ".word")
   1258     return ParseDirectiveWord(2, DirectiveID.getLoc());
   1259   if (IDVal == ".llong")
   1260     return ParseDirectiveWord(8, DirectiveID.getLoc());
   1261   if (IDVal == ".tc")
   1262     return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
   1263   if (IDVal == ".machine")
   1264     return ParseDirectiveMachine(DirectiveID.getLoc());
   1265   return true;
   1266 }
   1267 
   1268 /// ParseDirectiveWord
   1269 ///  ::= .word [ expression (, expression)* ]
   1270 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
   1271   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   1272     for (;;) {
   1273       const MCExpr *Value;
   1274       if (getParser().parseExpression(Value))
   1275         return true;
   1276 
   1277       getParser().getStreamer().EmitValue(Value, Size);
   1278 
   1279       if (getLexer().is(AsmToken::EndOfStatement))
   1280         break;
   1281 
   1282       if (getLexer().isNot(AsmToken::Comma))
   1283         return Error(L, "unexpected token in directive");
   1284       Parser.Lex();
   1285     }
   1286   }
   1287 
   1288   Parser.Lex();
   1289   return false;
   1290 }
   1291 
   1292 /// ParseDirectiveTC
   1293 ///  ::= .tc [ symbol (, expression)* ]
   1294 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
   1295   // Skip TC symbol, which is only used with XCOFF.
   1296   while (getLexer().isNot(AsmToken::EndOfStatement)
   1297          && getLexer().isNot(AsmToken::Comma))
   1298     Parser.Lex();
   1299   if (getLexer().isNot(AsmToken::Comma))
   1300     return Error(L, "unexpected token in directive");
   1301   Parser.Lex();
   1302 
   1303   // Align to word size.
   1304   getParser().getStreamer().EmitValueToAlignment(Size);
   1305 
   1306   // Emit expressions.
   1307   return ParseDirectiveWord(Size, L);
   1308 }
   1309 
   1310 /// ParseDirectiveMachine
   1311 ///  ::= .machine [ cpu | "push" | "pop" ]
   1312 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
   1313   if (getLexer().isNot(AsmToken::Identifier) &&
   1314       getLexer().isNot(AsmToken::String))
   1315     return Error(L, "unexpected token in directive");
   1316 
   1317   StringRef CPU = Parser.getTok().getIdentifier();
   1318   Parser.Lex();
   1319 
   1320   // FIXME: Right now, the parser always allows any available
   1321   // instruction, so the .machine directive is not useful.
   1322   // Implement ".machine any" (by doing nothing) for the benefit
   1323   // of existing assembler code.  Likewise, we can then implement
   1324   // ".machine push" and ".machine pop" as no-op.
   1325   if (CPU != "any" && CPU != "push" && CPU != "pop")
   1326     return Error(L, "unrecognized machine type");
   1327 
   1328   if (getLexer().isNot(AsmToken::EndOfStatement))
   1329     return Error(L, "unexpected token in directive");
   1330 
   1331   return false;
   1332 }
   1333 
   1334 /// Force static initialization.
   1335 extern "C" void LLVMInitializePowerPCAsmParser() {
   1336   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
   1337   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
   1338   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
   1339 }
   1340 
   1341 #define GET_REGISTER_MATCHER
   1342 #define GET_MATCHER_IMPLEMENTATION
   1343 #include "PPCGenAsmMatcher.inc"
   1344 
   1345 // Define this matcher function after the auto-generated include so we
   1346 // have the match class enum definitions.
   1347 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
   1348                                                   unsigned Kind) {
   1349   // If the kind is a token for a literal immediate, check if our asm
   1350   // operand matches. This is for InstAliases which have a fixed-value
   1351   // immediate in the syntax.
   1352   int64_t ImmVal;
   1353   switch (Kind) {
   1354     case MCK_0: ImmVal = 0; break;
   1355     case MCK_1: ImmVal = 1; break;
   1356     default: return Match_InvalidOperand;
   1357   }
   1358 
   1359   PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
   1360   if (Op->isImm() && Op->getImm() == ImmVal)
   1361     return Match_Success;
   1362 
   1363   return Match_InvalidOperand;
   1364 }
   1365 
   1366