| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.h | 28 ARMRegisterInfo(const ARMSubtarget &STI);
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| ARMInstrInfo.h | 28 explicit ARMInstrInfo(const ARMSubtarget &STI);
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| Thumb2RegisterInfo.h | 28 Thumb2RegisterInfo(const ARMSubtarget &STI);
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| Thumb1InstrInfo.h | 27 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
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| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.h | 23 explicit MipsSEFrameLowering(const MipsSubtarget &STI)
24 : MipsFrameLowering(STI, STI.hasMips64() ? 16 : 8) {}
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| MipsFrameLowering.h | 26 const MipsSubtarget &STI;
29 explicit MipsFrameLowering(const MipsSubtarget &sti, unsigned Alignment)
30 : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {}
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| Mips16FrameLowering.h | 22 explicit Mips16FrameLowering(const MipsSubtarget &STI)
23 : MipsFrameLowering(STI, 8) {}
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 32 const MCSubtargetInfo &STI,
36 const MCSubtargetInfo &STI,
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| AMDGPUMCTargetDesc.cpp | 69 const MCSubtargetInfo &STI) {
74 const MCSubtargetInfo &STI,
76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
77 return createSIMCCodeEmitter(MCII, STI, Ctx);
79 return createR600MCCodeEmitter(MCII, STI, Ctx);
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 32 const MCSubtargetInfo &STI,
36 const MCSubtargetInfo &STI,
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| AMDGPUMCTargetDesc.cpp | 69 const MCSubtargetInfo &STI) {
74 const MCSubtargetInfo &STI,
76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
77 return createSIMCCodeEmitter(MCII, STI, Ctx);
79 return createR600MCCodeEmitter(MCII, STI, Ctx);
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 36 const MCSubtargetInfo &STI);
40 const MCSubtargetInfo &STI,
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| AMDGPUMCTargetDesc.cpp | 70 const MCSubtargetInfo &STI) {
76 const MCSubtargetInfo &STI,
78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
81 return createR600MCCodeEmitter(MCII, MRI, STI);
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| R600MCCodeEmitter.cpp | 38 const MCSubtargetInfo &STI;
43 const MCSubtargetInfo &sti)
44 : MCII(mcii), MRI(mri), STI(sti) { }
86 const MCSubtargetInfo &STI) {
87 return new R600MCCodeEmitter(MCII, MRI, STI);
102 if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) {
135 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
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| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 37 const TargetSubtargetInfo *STI;
44 TargetSchedModel(): STI(0), TII(0) {}
51 void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
107 return STI->getWriteProcResBegin(SC);
110 return STI->getWriteProcResEnd(SC);
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| /external/llvm/include/llvm/MC/ |
| MCDisassembler.h | 59 MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0),
61 STI(STI), Symbolizer(0),
104 const MCSubtargetInfo &STI;
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| /external/llvm/tools/llvm-mc/ |
| Disassembler.h | 33 MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.h | 21 const HexagonSubtarget &STI;
25 explicit HexagonFrameLowering(const HexagonSubtarget &sti)
26 : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) {
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| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.h | 26 const MSP430Subtarget &STI;
29 explicit MSP430FrameLowering(const MSP430Subtarget &sti)
30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) {
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.h | 40 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.h | 40 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCTargetDesc.h | 54 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.h | 109 X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode,
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| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 55 const TargetSubtargetInfo *sti,
58 STI = sti;
60 STI->initInstrItins(InstrItins);
117 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
193 STI->getWriteLatencyEntry(SCDesc, DefIdx);
204 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
241 STI->getWriteLatencyEntry(SCDesc, DefIdx);
276 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
277 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.h | 40 const AArch64Subtarget &STI;
43 explicit AArch64FrameLowering(const AArch64Subtarget &sti)
45 STI(sti) {
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