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      1 //===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements a wrapper around MCSchedModel that allows the interface
     11 // to benefit from information currently only available in TargetInstrInfo.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #include "llvm/CodeGen/TargetSchedule.h"
     16 #include "llvm/Support/CommandLine.h"
     17 #include "llvm/Support/raw_ostream.h"
     18 #include "llvm/Target/TargetInstrInfo.h"
     19 #include "llvm/Target/TargetMachine.h"
     20 #include "llvm/Target/TargetRegisterInfo.h"
     21 #include "llvm/Target/TargetSubtargetInfo.h"
     22 
     23 using namespace llvm;
     24 
     25 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
     26   cl::desc("Use TargetSchedModel for latency lookup"));
     27 
     28 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
     29   cl::desc("Use InstrItineraryData for latency lookup"));
     30 
     31 bool TargetSchedModel::hasInstrSchedModel() const {
     32   return EnableSchedModel && SchedModel.hasInstrSchedModel();
     33 }
     34 
     35 bool TargetSchedModel::hasInstrItineraries() const {
     36   return EnableSchedItins && !InstrItins.isEmpty();
     37 }
     38 
     39 static unsigned gcd(unsigned Dividend, unsigned Divisor) {
     40   // Dividend and Divisor will be naturally swapped as needed.
     41   while(Divisor) {
     42     unsigned Rem = Dividend % Divisor;
     43     Dividend = Divisor;
     44     Divisor = Rem;
     45   };
     46   return Dividend;
     47 }
     48 static unsigned lcm(unsigned A, unsigned B) {
     49   unsigned LCM = (uint64_t(A) * B) / gcd(A, B);
     50   assert((LCM >= A && LCM >= B) && "LCM overflow");
     51   return LCM;
     52 }
     53 
     54 void TargetSchedModel::init(const MCSchedModel &sm,
     55                             const TargetSubtargetInfo *sti,
     56                             const TargetInstrInfo *tii) {
     57   SchedModel = sm;
     58   STI = sti;
     59   TII = tii;
     60   STI->initInstrItins(InstrItins);
     61 
     62   unsigned NumRes = SchedModel.getNumProcResourceKinds();
     63   ResourceFactors.resize(NumRes);
     64   ResourceLCM = SchedModel.IssueWidth;
     65   for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
     66     unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
     67     if (NumUnits > 0)
     68       ResourceLCM = lcm(ResourceLCM, NumUnits);
     69   }
     70   MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
     71   for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
     72     unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
     73     ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
     74   }
     75 }
     76 
     77 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI,
     78                                           const MCSchedClassDesc *SC) const {
     79   if (hasInstrItineraries()) {
     80     int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
     81     return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
     82   }
     83   if (hasInstrSchedModel()) {
     84     if (!SC)
     85       SC = resolveSchedClass(MI);
     86     if (SC->isValid())
     87       return SC->NumMicroOps;
     88   }
     89   return MI->isTransient() ? 0 : 1;
     90 }
     91 
     92 // The machine model may explicitly specify an invalid latency, which
     93 // effectively means infinite latency. Since users of the TargetSchedule API
     94 // don't know how to handle this, we convert it to a very large latency that is
     95 // easy to distinguish when debugging the DAG but won't induce overflow.
     96 static unsigned capLatency(int Cycles) {
     97   return Cycles >= 0 ? Cycles : 1000;
     98 }
     99 
    100 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
    101 /// evaluation of predicates that depend on instruction operands or flags.
    102 const MCSchedClassDesc *TargetSchedModel::
    103 resolveSchedClass(const MachineInstr *MI) const {
    104 
    105   // Get the definition's scheduling class descriptor from this machine model.
    106   unsigned SchedClass = MI->getDesc().getSchedClass();
    107   const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
    108   if (!SCDesc->isValid())
    109     return SCDesc;
    110 
    111 #ifndef NDEBUG
    112   unsigned NIter = 0;
    113 #endif
    114   while (SCDesc->isVariant()) {
    115     assert(++NIter < 6 && "Variants are nested deeper than the magic number");
    116 
    117     SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
    118     SCDesc = SchedModel.getSchedClassDesc(SchedClass);
    119   }
    120   return SCDesc;
    121 }
    122 
    123 /// Find the def index of this operand. This index maps to the machine model and
    124 /// is independent of use operands. Def operands may be reordered with uses or
    125 /// merged with uses without affecting the def index (e.g. before/after
    126 /// regalloc). However, an instruction's def operands must never be reordered
    127 /// with respect to each other.
    128 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
    129   unsigned DefIdx = 0;
    130   for (unsigned i = 0; i != DefOperIdx; ++i) {
    131     const MachineOperand &MO = MI->getOperand(i);
    132     if (MO.isReg() && MO.isDef())
    133       ++DefIdx;
    134   }
    135   return DefIdx;
    136 }
    137 
    138 /// Find the use index of this operand. This is independent of the instruction's
    139 /// def operands.
    140 ///
    141 /// Note that uses are not determined by the operand's isUse property, which
    142 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
    143 /// a "use". The machine model allows an operand to be both a Def and Use.
    144 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
    145   unsigned UseIdx = 0;
    146   for (unsigned i = 0; i != UseOperIdx; ++i) {
    147     const MachineOperand &MO = MI->getOperand(i);
    148     if (MO.isReg() && MO.readsReg())
    149       ++UseIdx;
    150   }
    151   return UseIdx;
    152 }
    153 
    154 // Top-level API for clients that know the operand indices.
    155 unsigned TargetSchedModel::computeOperandLatency(
    156   const MachineInstr *DefMI, unsigned DefOperIdx,
    157   const MachineInstr *UseMI, unsigned UseOperIdx) const {
    158 
    159   if (!hasInstrSchedModel() && !hasInstrItineraries())
    160     return TII->defaultDefLatency(&SchedModel, DefMI);
    161 
    162   if (hasInstrItineraries()) {
    163     int OperLatency = 0;
    164     if (UseMI) {
    165       OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
    166                                            UseMI, UseOperIdx);
    167     }
    168     else {
    169       unsigned DefClass = DefMI->getDesc().getSchedClass();
    170       OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
    171     }
    172     if (OperLatency >= 0)
    173       return OperLatency;
    174 
    175     // No operand latency was found.
    176     unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
    177 
    178     // Expected latency is the max of the stage latency and itinerary props.
    179     // Rather than directly querying InstrItins stage latency, we call a TII
    180     // hook to allow subtargets to specialize latency. This hook is only
    181     // applicable to the InstrItins model. InstrSchedModel should model all
    182     // special cases without TII hooks.
    183     InstrLatency = std::max(InstrLatency,
    184                             TII->defaultDefLatency(&SchedModel, DefMI));
    185     return InstrLatency;
    186   }
    187   // hasInstrSchedModel()
    188   const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
    189   unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
    190   if (DefIdx < SCDesc->NumWriteLatencyEntries) {
    191     // Lookup the definition's write latency in SubtargetInfo.
    192     const MCWriteLatencyEntry *WLEntry =
    193       STI->getWriteLatencyEntry(SCDesc, DefIdx);
    194     unsigned WriteID = WLEntry->WriteResourceID;
    195     unsigned Latency = capLatency(WLEntry->Cycles);
    196     if (!UseMI)
    197       return Latency;
    198 
    199     // Lookup the use's latency adjustment in SubtargetInfo.
    200     const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
    201     if (UseDesc->NumReadAdvanceEntries == 0)
    202       return Latency;
    203     unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
    204     int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
    205     if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
    206       return 0;
    207     return Latency - Advance;
    208   }
    209   // If DefIdx does not exist in the model (e.g. implicit defs), then return
    210   // unit latency (defaultDefLatency may be too conservative).
    211 #ifndef NDEBUG
    212   if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
    213       && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
    214     std::string Err;
    215     raw_string_ostream ss(Err);
    216     ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
    217        << *DefMI;
    218     report_fatal_error(ss.str());
    219   }
    220 #endif
    221   // FIXME: Automatically giving all implicit defs defaultDefLatency is
    222   // undesirable. We should only do it for defs that are known to the MC
    223   // desc like flags. Truly implicit defs should get 1 cycle latency.
    224   return DefMI->isTransient() ? 0 : TII->defaultDefLatency(&SchedModel, DefMI);
    225 }
    226 
    227 unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
    228   // For the itinerary model, fall back to the old subtarget hook.
    229   // Allow subtargets to compute Bundle latencies outside the machine model.
    230   if (hasInstrItineraries() || MI->isBundle())
    231     return TII->getInstrLatency(&InstrItins, MI);
    232 
    233   if (hasInstrSchedModel()) {
    234     const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
    235     if (SCDesc->isValid()) {
    236       unsigned Latency = 0;
    237       for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
    238            DefIdx != DefEnd; ++DefIdx) {
    239         // Lookup the definition's write latency in SubtargetInfo.
    240         const MCWriteLatencyEntry *WLEntry =
    241           STI->getWriteLatencyEntry(SCDesc, DefIdx);
    242         Latency = std::max(Latency, capLatency(WLEntry->Cycles));
    243       }
    244       return Latency;
    245     }
    246   }
    247   return TII->defaultDefLatency(&SchedModel, MI);
    248 }
    249 
    250 unsigned TargetSchedModel::
    251 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
    252                      const MachineInstr *DepMI) const {
    253   if (SchedModel.MicroOpBufferSize <= 1)
    254     return 1;
    255 
    256   // MicroOpBufferSize > 1 indicates an out-of-order processor that can dispatch
    257   // WAW dependencies in the same cycle.
    258 
    259   // Treat predication as a data dependency for out-of-order cpus. In-order
    260   // cpus do not need to treat predicated writes specially.
    261   //
    262   // TODO: The following hack exists because predication passes do not
    263   // correctly append imp-use operands, and readsReg() strangely returns false
    264   // for predicated defs.
    265   unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
    266   const MachineFunction &MF = *DefMI->getParent()->getParent();
    267   const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
    268   if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
    269     return computeInstrLatency(DefMI);
    270 
    271   // If we have a per operand scheduling model, check if this def is writing
    272   // an unbuffered resource. If so, it treated like an in-order cpu.
    273   if (hasInstrSchedModel()) {
    274     const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
    275     if (SCDesc->isValid()) {
    276       for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
    277              *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
    278         if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->BufferSize)
    279           return 1;
    280       }
    281     }
    282   }
    283   return 0;
    284 }
    285