/external/qemu/ |
ppc-dis.c | 688 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 689 #define RA NSI + 1 693 /* As above, but 0 in the RA field means zero, not r0. */ 694 #define RA0 RA + 1 697 /* The RA field in the DQ form lq instruction, which has special 702 /* The RA field in a D or X form instruction which is an updating 703 load, which means that the RA field may not be zero and may not 708 /* The RA field in an lmw instruction, which has special value 713 /* The RA field in a D or X form instruction which is an updating 714 store or an updating floating point load, which means that the RA [all...] |
/external/qemu/tcg/ppc/ |
tcg-target.c | 397 #define RA(r) ((r)<<16) 407 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b)) 408 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b)) 449 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff)); 451 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff)); 453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff)); 461 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff)); 464 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0)); 493 tcg_out32 (s, LWZ | RT (0) | RA (reg)); 494 tcg_out32 (s, MTSPR | RA (0) | CTR) [all...] |
/external/smack/src/org/xbill/DNS/ |
Flags.java | 29 public static final byte RA = 8; 49 flags.add(RA, "ra");
|
/art/runtime/arch/mips/ |
registers_mips.cc | 28 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra", 31 if (rhs >= ZERO && rhs <= RA) {
|
context_mips.h | 43 SetGPR(RA, new_pc); 59 // Hold values for sp and ra (return address) if they are not located within a stack frame.
|
context_mips.cc | 36 gprs_[RA] = &ra_; 39 ra_ = MipsContext::kBadGprBase + RA;
|
registers_mips.h | 61 RA = 31, // Return address.
|
/external/qemu/tcg/ppc64/ |
tcg-target.c | 394 #define RA(r) ((r)<<16) 405 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b)) 406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b)) 443 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb) 447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb); 453 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff)); 455 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff)); 457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff)); 477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16) [all...] |
/external/clang/test/CodeGenCXX/ |
devirtualize-virtual-function-calls-final.cpp | 164 struct RA { 169 struct RC final : public RA { 185 return static_cast<RA*>(x)->f();
|
/external/llvm/lib/Target/Mips/ |
Mips16FrameLowering.cpp | 68 unsigned RA = MRI->getDwarfRegNum(Mips::RA, true); 69 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, RA, -4)); 107 // Registers RA, S0,S1 are the callee saved registers and they 113 // RA and return address is taken, because it has already been added in 115 // It's killed at the spill, unless the register is RA and return address 118 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA) 132 // Registers RA,S0,S1 are the callee saved registers and they will be restored 171 MF.getRegInfo().setPhysRegUsed(Mips::RA);
|
/external/llvm/lib/MC/ |
MCSubtargetInfo.cpp | 43 const MCReadAdvanceEntry *RA, 54 ReadAdvanceTable = RA;
|
/bionic/libc/arch-mips/include/machine/ |
regnum.h | 67 #define RA 31
|
/development/ndk/platforms/android-9/arch-mips/include/machine/ |
regnum.h | 67 #define RA 31
|
/prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/machine/ |
regnum.h | 67 #define RA 31
|
/prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/machine/ |
regnum.h | 67 #define RA 31
|
/prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/machine/ |
regnum.h | 67 #define RA 31
|
/prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/machine/ |
regnum.h | 67 #define RA 31
|
/prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/machine/ |
regnum.h | 67 #define RA 31
|
/prebuilts/python/darwin-x86/2.7.5/lib/python2.7/ |
Cookie.py | 492 RA = result.append 495 RA("%s=%s" % (self.key, self.coded_value)) 506 RA("%s=%s" % (self._reserved[K], _getdate(V))) 508 RA("%s=%d" % (self._reserved[K], V)) 510 RA(str(self._reserved[K])) 512 RA(str(self._reserved[K])) 514 RA("%s=%s" % (self._reserved[K], V))
|
/prebuilts/python/linux-x86/2.7.5/lib/python2.7/ |
Cookie.py | 492 RA = result.append 495 RA("%s=%s" % (self.key, self.coded_value)) 506 RA("%s=%s" % (self._reserved[K], _getdate(V))) 508 RA("%s=%d" % (self._reserved[K], V)) 510 RA(str(self._reserved[K])) 512 RA(str(self._reserved[K])) 514 RA("%s=%s" % (self._reserved[K], V))
|
/external/llvm/lib/Transforms/IPO/ |
DeadArgumentElimination.cpp | 158 void MarkValue(const RetOrArg &RA, Liveness L, 160 void MarkLive(const RetOrArg &RA); 162 void PropagateLiveness(const RetOrArg &RA); 638 /// MarkValue - This function marks the liveness of RA depending on L. If L is 640 /// such that RA will be marked live if any use in MaybeLiveUses gets marked 642 void DAE::MarkValue(const RetOrArg &RA, Liveness L, 645 case Live: MarkLive(RA); break; 652 Uses.insert(std::make_pair(*UI, RA)); 677 void DAE::MarkLive(const RetOrArg &RA) { 678 if (LiveFunctions.count(RA.F) [all...] |
/external/llvm/utils/TableGen/ |
FixedLenDecoderEmitter.cpp | 468 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex, [all...] |
/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
PPCMCTargetDesc.cpp | 48 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; 51 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
|
/art/compiler/dex/quick/x86/ |
x86_lir.h | 236 // RA - Register Array - opcode reg, [base + index * scale + disp] 250 opcode ## 8RR, opcode ## 8RM, opcode ## 8RA, opcode ## 8RT, \ 253 opcode ## 16RR, opcode ## 16RM, opcode ## 16RA, opcode ## 16RT, \ 257 opcode ## 32RR, opcode ## 32RM, opcode ## 32RA, opcode ## 32RT, \ 318 opcode ## RR, opcode ## RM, opcode ## RA 386 kRegReg, kRegMem, kRegArray, kRegThread, // RR, RM, RA and RT instruction kinds.
|
/external/llvm/include/llvm/MC/ |
MCSubtargetInfo.h | 55 const MCReadAdvanceEntry *RA,
|