/system/core/libpixelflinger/codeflinger/ |
MIPSAssembler.h | 70 virtual uint32_t reg_reg(int Rm, int type, int Rs); 94 int Rd, int Rm, int Rs, int Rn); 96 int Rd, int Rm, int Rs); 98 int RdLo, int RdHi, int Rm, int Rs); 100 int RdLo, int RdHi, int Rm, int Rs); 102 int RdLo, int RdHi, int Rm, int Rs); 104 int RdLo, int RdHi, int Rm, int Rs); 148 int Rd, int Rm, int Rs); 150 int Rd, int Rm, int Rs); 152 int Rd, int Rm, int Rs, int Rn) [all...] |
ARMAssemblerInterface.h | 83 virtual uint32_t reg_reg(int Rm, int type, int Rs) = 0; 128 int Rd, int Rm, int Rs, int Rn) = 0; 130 int Rd, int Rm, int Rs) = 0; 132 int RdLo, int RdHi, int Rm, int Rs) = 0; 134 int RdLo, int RdHi, int Rm, int Rs) = 0; 136 int RdLo, int RdHi, int Rm, int Rs) = 0; 138 int RdLo, int RdHi, int Rm, int Rs) = 0; 204 int Rd, int Rm, int Rs) = 0; 206 int Rd, int Rm, int Rs) = 0; 208 int Rd, int Rm, int Rs, int Rn) = 0 [all...] |
ARMAssemblerProxy.h | 61 virtual uint32_t reg_reg(int Rm, int type, int Rs); 83 int Rd, int Rm, int Rs, int Rn); 85 int Rd, int Rm, int Rs); 87 int RdLo, int RdHi, int Rm, int Rs); 89 int RdLo, int RdHi, int Rm, int Rs); 91 int RdLo, int RdHi, int Rm, int Rs); 93 int RdLo, int RdHi, int Rm, int Rs); 136 int Rd, int Rm, int Rs); 138 int Rd, int Rm, int Rs); 140 int Rd, int Rm, int Rs, int Rn) [all...] |
MIPSAssembler.cpp | 248 uint32_t ArmToMipsAssembler::reg_reg(int Rm, int type, int Rs) 614 int Rd, int Rm, int Rs, int Rn) { 618 mMips->MUL(R_at, Rm, Rs); 627 int Rd, int Rm, int Rs) { 629 mMips->MUL(Rd, Rm, Rs); 637 int RdLo, int RdHi, int Rm, int Rs) { 639 mMips->MULT(Rm, Rs); 650 int RdLo, int RdHi, int Rm, int Rs) { 652 "UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs); 654 // (RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm [all...] |
ARMAssemblerProxy.cpp | 103 uint32_t ARMAssemblerProxy::reg_reg(int Rm, int type, int Rs) 105 return mTarget->reg_reg(Rm, type, Rs); 166 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) { 167 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn); 169 void ARMAssemblerProxy::MUL(int cc, int s, int Rd, int Rm, int Rs) { 170 mTarget->MUL(cc, s, Rd, Rm, Rs); 173 int RdLo, int RdHi, int Rm, int Rs) { 174 mTarget->UMULL(cc, s, RdLo, RdHi, Rm, Rs); 177 int RdLo, int RdHi, int Rm, int Rs) { 178 mTarget->UMUAL(cc, s, RdLo, RdHi, Rm, Rs); [all...] |
ARMAssembler.cpp | 229 int Rd, int Rm, int Rs, int Rn) { 230 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; } 231 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn); 233 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm; 236 int Rd, int Rm, int Rs) { 237 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; } 238 LOG_FATAL_IF(Rd==Rm, "MUL(r%u,r%u,r%u)", Rd,Rm,Rs); 239 *mPC++ = (cc<<28) | (s<<20) | (Rd<<16) | (Rs<<8) | 0x90 | Rm [all...] |
ARMAssembler.h | 72 virtual uint32_t reg_reg(int Rm, int type, int Rs); 94 int Rd, int Rm, int Rs, int Rn); 96 int Rd, int Rm, int Rs); 98 int RdLo, int RdHi, int Rm, int Rs); 100 int RdLo, int RdHi, int Rm, int Rs); 102 int RdLo, int RdHi, int Rm, int Rs); 104 int RdLo, int RdHi, int Rm, int Rs); 149 int Rd, int Rm, int Rs); 151 int Rd, int Rm, int Rs); 153 int Rd, int Rm, int Rs, int Rn) [all...] |
GGLAssembler.cpp | 392 int Rs = scratches.obtain(); 394 CONTEXT_LOAD(Rs, state.buffers.color.stride); 396 SMLABB(AL, Rs, Ry, Rs, Rx); // Rs = Rx + Ry*Rs 397 base_offset(parts.cbPtr, parts.cbPtr, Rs); 398 scratches.recycle(Rs); 428 int Rs = dzdx; 430 CONTEXT_LOAD(Rs, state.buffers.depth.stride) [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64RegisterInfo.h | 40 RegScavenger *Rs = NULL) const;
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/development/tools/findunused/ |
findunusedstrings | 32 for i in $(grep -Rs "\(string\|plurals\) name=" res | sed 's/.*string name=\"//' | sed 's/.*plurals name=\"//'|sed 's/".*$//'|sort -u)
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/frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
rate_control.h | 36 Int Rs; /*bit rate for the sequence (or segment) e.g., 24000 bits/sec */
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/external/eigen/Eigen/src/UmfPackSupport/ |
UmfPackSupport.h | 84 int P[], int Q[], double Dx[], int *do_recip, double Rs[], void *Numeric) 86 return umfpack_di_get_numeric(Lp,Lj,Lx,Up,Ui,Ux,P,Q,Dx,do_recip,Rs,Numeric); 90 int P[], int Q[], std::complex<double> Dx[], int *do_recip, double Rs[], void *Numeric) 96 Dx?&dx0_real:0,0,do_recip,Rs,Numeric);
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/external/chromium_org/third_party/mesa/src/src/mesa/swrast/ |
s_blend.c | 483 const GLfloat Rs = rgba[i][RCOMP]; 557 sR = Rs; 562 sR = 1.0F - Rs; 635 dR = Rs; 640 dR = 1.0F - Rs; 743 r = Rs * sR + Rd * dR; 749 r = Rs * sR - Rd * dR; 755 r = Rd * dR - Rs * sR; 761 r = MIN2( Rd, Rs ); 766 r = MAX2( Rd, Rs ); [all...] |
/external/mesa3d/src/mesa/swrast/ |
s_blend.c | 483 const GLfloat Rs = rgba[i][RCOMP]; 557 sR = Rs; 562 sR = 1.0F - Rs; 635 dR = Rs; 640 dR = 1.0F - Rs; 743 r = Rs * sR + Rd * dR; 749 r = Rs * sR - Rd * dR; 755 r = Rd * dR - Rs * sR; 761 r = MIN2( Rd, Rs ); 766 r = MAX2( Rd, Rs ); [all...] |
/frameworks/av/media/libstagefright/codecs/avc/enc/src/ |
avcenc_int.h | 256 int Rs; /*bit rate for the sequence (or segment) e.g., 24000 bits/sec */
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/external/qemu/ |
trace.c | 895 int Rs = (insn >> 8) & 15; 905 result += 2 + _interlock_use(Rm) + _interlock_use(Rs); 910 int Rs = (insn >> 8) & 15; 920 result += 3 + _interlock_use(Rm) + _interlock_use(Rs); [all...] |
/external/chromium_org/v8/src/arm/ |
disasm-arm.cc | 242 int rs = instr->RsValue(); local 245 PrintRegister(rs); 338 } else if (format[1] == 's') { // 'rs: Rs register 743 Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 747 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 750 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); 753 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 756 Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd"); 765 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs> [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMCodeEmitter.cpp | [all...] |
/external/v8/src/arm/ |
disasm-arm.cc | 236 int rs = instr->RsValue(); local 239 PrintRegister(rs); 332 } else if (format[1] == 's') { // 'rs: Rs register 693 Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 696 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 699 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); 707 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs> 708 Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs"); [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/chromium_org/third_party/libjingle/source/talk/media/testdata/ |
h264-svc-99-640x360.rtpdump | [all...] |