| /external/libffi/linux-x86/ |
| ffi.h | 6 #define X86 1
9 #include "../src/x86/ffitarget.h"
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | 1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
49 " fuse, but the X86 backend currently can't"),
95 ? X86::ADJCALLSTACKDOWN64
96 : X86::ADJCALLSTACKDOWN32),
98 ? X86::ADJCALLSTACKUP64
99 : X86::ADJCALLSTACKUP32)),
103 { X86::ADC32ri, X86::ADC32mi, 0 }
[all...] |
| X86RegisterInfo.cpp | 1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
12 // on X86.
17 #include "X86.h"
54 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
59 ? X86::RIP : X86::EIP),
63 ? X86::RIP : X86::EIP)),
74 StackPtr = X86::RSP
[all...] |
| X86FloatingPoint.cpp | 26 #define DEBUG_TYPE "x86-codegen"
27 #include "X86.h"
72 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
119 if (Reg < X86::FP0 || Reg > X86::FP6)
121 Mask |= 1 << (Reg - X86::FP0);
214 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
221 /// getSTReg - Return the X86::ST(i) register which contains the specified
224 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
253 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg)
[all...] |
| X86MCInstLower.cpp | 1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
247 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
265 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
266 if (Op0 == X86::AX && Op1 == X86::AL)
267 NewOpcode = X86::CBW
[all...] |
| X86Relocations.h | 1 //===-- X86Relocations.h - X86 Code Relocations -----------------*- C++ -*-===//
10 // This file defines the X86 target-specific relocation types.
20 namespace X86 {
21 /// RelocationType - An enum for the x86 relocation codes. Note that
22 /// the terminology here doesn't follow x86 convention - word means
24 /// by JIT or ObjectCode emitters, this is transparent to the x86 code
|
| X86FrameLowering.cpp | 1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
61 return X86::SUB64ri8;
62 return X86::SUB64ri32;
65 return X86::SUB32ri8;
66 return X86::SUB32ri;
73 return X86::ADD64ri8;
74 return X86::ADD64ri32;
77 return X86::ADD32ri8;
78 return X86::ADD32ri
[all...] |
| X86Subtarget.cpp | 1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
68 // X86-64 in PIC mode.
76 // target is x86-64 or the symbol is definitely defined in the current
207 if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
208 if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
209 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
210 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
211 if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
212 if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);
[all...] |
| X86FixupLEAs.cpp | 16 #define DEBUG_TYPE "x86-fixup-LEAs"
17 #include "X86.h"
42 virtual const char *getPassName() const { return "X86 Atom LEA Fixup";}
100 case X86::MOV32rr:
101 case X86::MOV64rr: {
105 TII->get( MI->getOpcode() == X86::MOV32rr ? X86::LEA32r : X86::LEA64r))
111 case X86::ADD64ri32:
112 case X86::ADD64ri8
[all...] |
| X86FastISel.cpp | 1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
16 #include "X86.h"
167 // We only handle legal types. For example, on x86-32 the instruction
168 // selector contains all of the 64-bit instructions from x86-64,
188 Opc = X86::MOV8rm;
189 RC = &X86::GR8RegClass;
192 Opc = X86::MOV16rm;
193 RC = &X86::GR16RegClass;
196 Opc = X86::MOV32rm
[all...] |
| X86ISelDAGToDAG.cpp | 1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86.h"
91 return RegNode->getReg() == X86::RIP;
140 /// ISel - X86 specific code to select X86 machine instructions for
159 return "X86 DAG->DAG Instruction Selection";
489 // late" legalization of these inline with the X86 isel pass
[all...] |
| X86CodeEmitter.cpp | 1 //===-- X86CodeEmitter.cpp - Convert X86 code to machine code -------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86.h"
62 return "X86 Machine Code Emitter";
121 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
149 if (Desc.getOpcode() == X86::MOVPC32r)
150 emitInstruction(*I, &II->get(X86::POP32r));
159 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
161 /// size, and 3) use of X86-64 extended registers
[all...] |
| X86VZeroUpper.cpp | 10 // This file defines the pass which inserts x86 AVX vzeroupper instructions
17 #define DEBUG_TYPE "x86-vzeroupper"
18 #include "X86.h"
41 virtual const char *getPassName() const { return "X86 vzeroupper inserter";}
108 return (Reg >= X86::YMM0 && Reg <= X86::YMM31);
112 return (Reg >= X86::ZMM0 && Reg <= X86::ZMM31);
125 for (unsigned reg = X86::YMM0; reg < X86::YMM31; ++reg)
[all...] |
| X86SelectionDAGInfo.cpp | 1 //===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===//
14 #define DEBUG_TYPE "x86-selectiondag-info"
96 ValReg = X86::AX;
101 ValReg = X86::EAX;
106 ValReg = X86::RAX;
112 ValReg = X86::AL;
129 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
133 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
134 X86::ECX,
137 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86AsmBackend.cpp | 1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
34 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
35 cl::desc("Disable relaxation of arithmetic instruction for X86"));
47 case X86::reloc_riprel_4byte:
48 case X86::reloc_riprel_4byte_movq_load:
49 case X86::reloc_signed_4byte:
50 case X86::reloc_global_offset_table:
75 return X86::NumTargetFixupKinds;
79 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
130 case X86::JAE_1: return X86::JAE_4
[all...] |
| X86BaseInfo.h | 1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
11 // the X86 target useful for the compiler back-end and the MC libraries.
27 namespace X86 {
44 } // end namespace X86;
53 // X86 Specific MachineOperand flags.
70 /// See the X86-64 ELF ABI supplement for more details.
77 /// See the X86-64 ELF ABI supplement for more details.
85 /// See the X86-64 ELF ABI supplement for more details.
92 /// See the X86-64 ELF ABI supplement for more details.
109 /// block for the symbol. Used in the x86-64 local dynamic TLS access model
[all...] |
| X86FixupKinds.h | 1 //===-- X86FixupKinds.h - X86 Specific Fixup Entries ------------*- C++ -*-===//
16 namespace X86 {
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 10 // This defines functionality used to emit comments about X86 instructions to
26 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
36 case X86::INSERTPSrr:
37 case X86::VINSERTPSrr:
44 case X86::MOVLHPSrr:
45 case X86::VMOVLHPSrr:
52 case X86::MOVHLPSrr:
53 case X86::VMOVHLPSrr:
60 case X86::PALIGNR128rr:
61 case X86::VPALIGNR128rr
[all...] |
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.eclipse.equinox.launcher.gtk.linux.x86_1.1.2.R36x_v20101019_1345/ |
| launcher.gtk.linux.x86.properties | 11 pluginName = Equinox Launcher Linux X86 Fragment
|
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.eclipse.equinox.launcher.win32.win32.x86_1.1.2.R36x_v20101019_1345/ |
| launcher.win32.win32.x86.properties | 11 pluginName = Equinox Launcher Win32 X86 Fragment
|
| /external/llvm/host/include/llvm/Config/ |
| Targets.def | 28 LLVM_TARGET(X86)
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
10 // This file is part of the X86 Disassembler.
56 namespace X86 {
159 #define ENTRY(x) X86::x,
247 // By default sign-extend all X86 immediates based on their encoding.
255 // Special case those X86 instructions that use the imm8 as a set of
257 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
258 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &
[all...] |
| /external/chromium_org/third_party/WebKit/Tools/Scripts/webkitruby/check-for-inappropriate-macros-in-external-headers-tests/resources/Fake.framework/Headers/ |
| Fail.h | 4 #if CPU(X86)
|
| /external/llvm/ |
| Android.mk | 56 # X86 Code Generation Libraries
58 lib/Target/X86 \
59 lib/Target/X86/AsmParser \
60 lib/Target/X86/InstPrinter \
61 lib/Target/X86/Disassembler \
62 lib/Target/X86/MCTargetDesc \
63 lib/Target/X86/TargetInfo \
64 lib/Target/X86/Utils
|
| /external/valgrind/main/VEX/auxprogs/ |
| genoffsets.c | 82 // x86
83 GENOFFSET(X86,x86,EAX);
84 GENOFFSET(X86,x86,EBX);
85 GENOFFSET(X86,x86,ECX);
86 GENOFFSET(X86,x86,EDX);
87 GENOFFSET(X86,x86,ESI)
[all...] |
