| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 206 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
214 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
222 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
229 /// should be 2, 3 or 4. The opcode array specifies the instructions used
305 // opcode and that it has a immediate integer right operand.
442 unsigned Opcode = MCID.getOpcode();
443 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
458 return TII->isFpMLxInstruction(Opcode);
816 unsigned Opcode = Op->getOpcode()
[all...] |
| ARMLoadStoreOptimizer.cpp | 94 int Offset, unsigned Base, bool BaseKill, int Opcode,
107 int Opcode,
114 int Opcode, unsigned Size,
137 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
138 switch (Opcode) {
139 default: llvm_unreachable("Unhandled opcode!");
208 AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
209 switch (Opcode) {
210 default: llvm_unreachable("Unhandled opcode!");
285 int Opcode, ARMCC::CondCodes Pred
[all...] |
| ARMBaseInstrInfo.cpp | 59 uint16_t MLxOpc; // MLA / MLS opcode
60 uint16_t MulOpc; // Expanded multiplication opcode
61 uint16_t AddSubOpc; // Expanded add / sub opcode
[all...] |
| ARMFastISel.cpp | 800 unsigned Opcode = Instruction::UserOp1;
806 Opcode = I->getOpcode();
810 Opcode = C->getOpcode();
820 switch (Opcode) {
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 245 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
246 switch (Opcode) {
752 unsigned opcode = NVPTXISD::StoreParam; local
754 opcode = NVPTXISD::StoreParamU32;
756 opcode = NVPTXISD::StoreParamS32;
757 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps, 5,
900 unsigned opcode; local
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 181 // Get opcode and regclass of the output for the given load instruction.
240 // Get opcode and regclass of the output for the given store instruction.
333 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
351 unsigned Opcode = Instruction::UserOp1;
358 Opcode = I->getOpcode();
362 Opcode = C->getOpcode();
372 switch (Opcode) {
611 unsigned Opcode = Instruction::UserOp1;
613 Opcode = I->getOpcode();
616 Opcode = C->getOpcode()
[all...] |
| X86ISelDAGToDAG.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 44 getTargetNodeName(unsigned Opcode) const
46 switch (Opcode)
693 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
696 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
700 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAndOrXor.cpp | 94 /// opcode and two operands into either a constant true or false, or a brand
106 /// opcode and two operands into either a FCmp instruction. isordered is passed
[all...] |
| InstructionCombining.cpp | 139 Instruction::BinaryOps Opcode = I.getOpcode();
140 if (Opcode != Instruction::Add &&
141 Opcode != Instruction::Sub) {
156 if (Opcode == Instruction::Add) {
202 Instruction::BinaryOps Opcode = I.getOpcode();
218 if (Op0 && Op0->getOpcode() == Opcode) {
224 if (Value *V = SimplifyBinOp(Opcode, B, C, TD)) {
247 if (Op1 && Op1->getOpcode() == Opcode) {
253 if (Value *V = SimplifyBinOp(Opcode, A, B, TD)) {
269 if (Op0 && Op0->getOpcode() == Opcode) {
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| IndVarSimplify.cpp | 787 unsigned Opcode = DU.NarrowUse->getOpcode();
788 switch (Opcode) {
[all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | 161 /// \returns The opcode if all of the Instructions in \p VL have the same
162 /// opcode, or zero.
167 unsigned Opcode = I0->getOpcode();
170 if (!I || Opcode != I->getOpcode())
173 return Opcode;
190 assert(Instruction::ExtractElement == getSameOpcode(VL) && "Invalid opcode");
616 unsigned Opcode = getSameOpcode(VL);
619 if (Opcode == Instruction::Load || Opcode == Instruction::Store) {
635 switch (Opcode) {
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.h | 340 gl_inst_opcode Opcode;
439 _mesa_num_inst_src_regs(gl_inst_opcode opcode);
442 _mesa_num_inst_dst_regs(gl_inst_opcode opcode);
445 _mesa_is_tex_instruction(gl_inst_opcode opcode);
451 _mesa_opcode_string(gl_inst_opcode opcode);
|
| /dalvik/libdex/ |
| DexOpcodes.h | 18 * Dalvik opcode information.
21 * automatically by the opcode-gen tool. Any edits to the generated
24 * See the file opcode-gen/README.txt for information about updating
34 * kMaxOpcodeValue: the highest possible raw (unpacked) opcode value
36 * kNumPackedOpcodes: the highest possible packed opcode value of a
37 * valid Dalvik opcode, plus one
42 // BEGIN(libdex-maximum-values); GENERATED AUTOMATICALLY BY opcode-gen
45 // END(libdex-maximum-values); GENERATED AUTOMATICALLY BY opcode-gen
58 * associated with each is the corresponding packed opcode number.
59 * This is different than the opcode value from the Dalvik bytecod
[all...] |
| /external/chromium_org/v8/src/arm/ |
| constants-arm.h | 149 enum Opcode {
625 return static_cast<Opcode>(Bits(24, 21));
627 inline Opcode OpcodeField() const {
628 return static_cast<Opcode>(BitField(24, 21));
|
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 137 module Opcode = struct
229 | Instruction of Opcode.t
382 external constexpr_opcode : llvalue -> Opcode.t = "llvm_constexpr_get_opcode"
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 459 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
460 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
635 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
636 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
[all...] |
| LegalizeVectorTypes.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 804 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
805 switch (Opcode) {
[all...] |
| /external/v8/src/arm/ |
| constants-arm.h | 190 enum Opcode {
634 return static_cast<Opcode>(Bits(24, 21));
636 inline Opcode OpcodeField() const {
637 return static_cast<Opcode>(BitField(24, 21));
|
| lithium-arm.h | 186 virtual Opcode opcode() const { return LInstruction::k##type; } \
216 enum Opcode {
224 virtual Opcode opcode() const = 0;
228 bool Is##type() const { return opcode() == k##type; }
233 // an opcode.
1108 virtual Opcode opcode() const { return LInstruction::kArithmeticD; } function in class:v8::internal::LArithmeticD
1125 virtual Opcode opcode() const { return LInstruction::kArithmeticT; } function in class:v8::internal::LArithmeticT
[all...] |
| /external/v8/src/ia32/ |
| lithium-ia32.h | 181 virtual Opcode opcode() const { return LInstruction::k##type; } \
211 enum Opcode {
219 virtual Opcode opcode() const = 0;
223 bool Is##type() const { return opcode() == k##type; }
228 // an opcode.
1109 virtual Opcode opcode() const { return LInstruction::kArithmeticD; } function in class:v8::internal::LArithmeticD
1130 virtual Opcode opcode() const { return LInstruction::kArithmeticT; } function in class:v8::internal::LArithmeticT
[all...] |
| /external/v8/src/mips/ |
| lithium-mips.h | 185 virtual Opcode opcode() const { return LInstruction::k##type; } \
215 enum Opcode {
223 virtual Opcode opcode() const = 0;
227 bool Is##type() const { return opcode() == k##type; }
232 // an opcode.
1088 virtual Opcode opcode() const { return LInstruction::kArithmeticD; } function in class:v8::internal::LArithmeticD
1105 virtual Opcode opcode() const { return LInstruction::kArithmeticT; function in class:v8::internal::LArithmeticT
[all...] |
