| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 347 // Insert instructions that spill eh data registers.
448 // It's killed at the spill, unless the register is RA and return address
456 // Insert the spill to the stack frame.
472 // Make sure the second register scavenger spill slot can be accessed with one
509 // Create spill slots for eh data registers if function calls eh_return.
514 // Add an emergency spill slot if a pseudo was expanded.
516 // The spill slot should be half the size of the accumulator. If target is
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| /art/runtime/mirror/ |
| art_method.h | 401 // Architecture-dependent register spill mask
412 // Architecture-dependent register spill mask
438 // When a register is promoted into a register, the spill mask holds which registers hold dex
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| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 32 /// spill locations) can be stored.
103 /// allowed to spill it anywhere it chooses.
132 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
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| /external/llvm/lib/CodeGen/ |
| RegAllocFast.cpp | 75 bool Dirty; // Register needs spill.
207 // Allocate a new stack object for this spill location...
282 // instruction, not on the spill.
315 DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
327 /// spillAll - Spill all dirty virtregs without killing them.
524 // Ignore the hint if we would have to spill a dirty register.
710 // we must spill and reallocate.
858 // Modify DBG_VALUE now that the value is in a spill slot.
868 DEBUG(dbgs() << "Modifying debug info due to spill:
[all...] |
| LiveStackAnalysis.cpp | 59 assert(Slot >= 0 && "Spill slot indice must be >= 0");
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| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.td | 152 // Register class for 64-bit mode, with a 64-bit spill slot size.
155 // spill slot is a stricter constraint than only requiring a 32-bit spill slot.
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| SparcSubtarget.cpp | 62 // 16 words for register window spill
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| /external/llvm/test/CodeGen/SystemZ/ |
| frame-17.ll | 6 ; 4-byte spill slot, rounded to 8 bytes. The frame size should be exactly
71 ; Same for doubles, except that the full spill slot is used.
132 ; The long double case needs a 16-byte spill slot.
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| frame-13.ll | 21 ; emergency spill slots at 160(%r15), the amount that we need to allocate
206 ; Repeat f2 in a case that needs the emergency spill slots (because all
242 ; And again with maximum register pressure. The only spill slots that the
245 ; spill a second register. This leads to an extra displacement of 8.
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| /dalvik/vm/mterp/x86/ |
| OP_EXECUTE_INLINE.S | 17 SPILL(rIBASE) # preserve rIBASE
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| OP_INSTANCE_OF.S | 21 SPILL(rIBASE) # preserve rIBASE
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| OP_NEW_INSTANCE.S | 16 SPILL(rIBASE)
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_ra.cpp | 285 void spill(Instruction *defi, Value *slot, LValue *);
707 SpillCodeInserter& spill; member in class:nv50_ir::GCRA
993 GCRA::GCRA(Function *fn, SpillCodeInserter& spill) :
996 spill(spill)
1153 (node->degree < node->degreeLimit) ? "" : "(spill)");
1171 // spill candidate
1180 ERROR("no viable spill candidates left\n");
1436 SpillCodeInserter::spill(Instruction *defi, Value *slot, LValue *lval) function in class:nv50_ir::SpillCodeInserter
[all...] |
| /external/chromium_org/ui/gfx/ |
| color_utils_unittest.cc | 71 // In a opt build on Linux, this was causing a register spill on my laptop
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| /external/chromium_org/v8/src/ |
| hydrogen-environment-liveness.h | 41 // unnecessary spill slot moves. Therefore it is beneficial to trim the
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| /external/chromium_org/v8/src/ia32/ |
| lithium-gap-resolver-ia32.h | 103 // If we had to spill on demand, the currently spilled register's
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| /external/libffi/src/ia64/ |
| ffi.c | 43 specific format used by ldf.fill/stf.spill. All we care about is
73 /* Store VALUE to ADDR in the current cpu implementation's fp spill format.
79 asm ("stf.spill %0 = %1%P0" : "=m" (*addr) : "f"(value));
82 fp spill format. As above, this must also be a macro. */
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| /external/llvm/include/llvm/CodeGen/PBQP/Heuristics/ |
| Briggs.h | 14 // then the node with the minimal spill-cost to degree ratio is removed.
32 /// problem represent storage options, with the first being the spill
40 /// the lowest estimated spill cost is selected and push to the solver stack
122 /// exception. Nodes whose spill cost (element 0 of their cost vector) is
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| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 103 // Determine the sizes of each callee-save spill areas and record which frame
104 // belongs to which callee-save spill areas.
159 // Determine starting offsets of spill areas.
272 // Move SP to start of FP callee save spill area.
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 234 // We can only schedule double loads if we spill contiguous callee-saved regs
235 // For instance, we cannot scheduled double-word loads if we spill r24,
289 // We can only schedule double loads if we spill contiguous callee-saved regs
290 // For instance, we cannot scheduled double-word loads if we spill r24,
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| /external/llvm/test/CodeGen/ARM/ |
| crash-O0.ll | 7 ; This function would crash RegAllocFast because it tried to spill %CPSR.
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_ra.cpp | 285 void spill(Instruction *defi, Value *slot, LValue *);
707 SpillCodeInserter& spill; member in class:nv50_ir::GCRA
993 GCRA::GCRA(Function *fn, SpillCodeInserter& spill) :
996 spill(spill)
1153 (node->degree < node->degreeLimit) ? "" : "(spill)");
1171 // spill candidate
1180 ERROR("no viable spill candidates left\n");
1436 SpillCodeInserter::spill(Instruction *defi, Value *slot, LValue *lval) function in class:nv50_ir::SpillCodeInserter
[all...] |
| /external/v8/src/ia32/ |
| lithium-gap-resolver-ia32.h | 103 // If we had to spill on demand, the currently spilled register's
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| /prebuilts/gcc/darwin-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/ |
| emit-rtl.h | 41 /* Set the attributes for MEM appropriate for a spill slot. */
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| /prebuilts/gcc/darwin-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/ |
| emit-rtl.h | 41 /* Set the attributes for MEM appropriate for a spill slot. */
|
