| /external/chromium_org/ppapi/native_client/src/untrusted/pnacl_irt_shim/ |
| pnacl_irt_shim.gyp | 15 'out_newlib_arm': '>(tc_lib_dir_pnacl_translate)/lib-arm/libpnacl_irt_shim.a',
33 ['target_arch=="arm"', {
37 '-arch', 'arm',
|
| /external/clang/test/CodeGen/ |
| arm-cc.c | 1 // REQUIRES: arm-registered-target
4 // RUN: %clang_cc1 -triple arm-none-linux-gnueabi -target-abi apcs-gnu -emit-llvm -w -o - %s | FileCheck -check-prefix=LINUX-APCS %s
5 // RUN: %clang_cc1 -triple arm-none-linux-gnueabi -target-abi aapcs -emit-llvm -w -o - %s | FileCheck -check-prefix=LINUX-AAPCS %s
|
| arm-vaarg-align.c | 1 // REQUIRES: arm-registered-target
2 // RUN: %clang_cc1 -triple arm -target-abi aapcs %s -emit-llvm -o - | FileCheck -check-prefix=AAPCS %s
3 // RUN: %clang_cc1 -triple arm -target-abi apcs-gnu %s -emit-llvm -o - | FileCheck -check-prefix=APCS-GNU %s
|
| arm-vector-align.c | 1 // REQUIRES: arm-registered-target
17 // CHECK: call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %{{.*}}, i32 16)
19 // CHECK: call void @llvm.arm.neon.vst1.v4f32(i8* %{{.*}}, <4 x float> %{{.*}}, i32 16)
|
| /external/clang/test/Driver/ |
| arm-darwin-builtin.c | 2 // RUX: clang -target x86_64-apple-darwin9 -arch arm -### -fsyntax-only %s 2> %t &&
7 // RUX: clang -target x86_64-apple-darwin9 -arch arm -### -fsyntax-only %s -fbuiltin-strcat -fbuiltin-strcpy 2> %t &&
11 // RUN: %clang -target x86_64-apple-darwin9 -arch arm -### -fsyntax-only %s -fbuiltin-strcat -fbuiltin-strcpy 2> %t
|
| /external/kernel-headers/original/asm-arm/ |
| procinfo.h | 2 * linux/include/asm-arm/procinfo.h
27 * arch/arm/mm/proc-*.S and arch/arm/kernel/head.S
|
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.cpp | 1 //===-- ARMRegisterInfo.cpp - ARM Register Information --------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
15 #include "ARM.h"
|
| Thumb1InstrInfo.cpp | 15 #include "ARM.h"
30 NopInst.setOpcode(ARM::tMOVr);
31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
56 assert((RC == &ARM::tGPRRegClass ||
60 if (RC == &ARM::tGPRRegClass ||
73 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
84 assert((RC == &ARM::tGPRRegClass |
[all...] |
| ARMFastISel.cpp | 1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
16 #include "ARM.h"
246 if (MO.getReg() == ARM::CPSR)
277 // Are we NEON in ARM mode and have a predicate operand? If so, I know
283 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
497 TII.get(ARM::VMOVSR), MoveReg)
507 TII.get(ARM::VMOVRS), MoveReg)
526 Opc = ARM::FCONSTD;
529 Opc = ARM::FCONSTS
[all...] |
| /external/llvm/ |
| shared_llvm.mk | 67 # Host build pulls in all ARM, Mips, X86 components.
92 # Device build selectively pulls in ARM, Mips, X86 components.
96 ifeq ($(TARGET_ARCH),arm)
|
| /external/llvm/test/CodeGen/ARM/ |
| 2010-05-18-PostIndexBug.ll | 1 ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s -check-prefix=ARM
9 ; ARM-LABEL: t:
10 ; ARM: str r2, [r1], r0
|
| 2010-06-11-vmovdrr-bitcast.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon
15 tail call void @llvm.arm.neon.vst2.v8i8(i8* %b, <8 x i8> %tmp16.i, <8 x i8> %tmp20.i, i32 1) nounwind
19 declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind
|
| 2011-10-26-memset-inline.ll | 1 ; Make sure short memsets on ARM lower to stores, even when optimizing for size.
2 ; RUN: llc -march=arm < %s | FileCheck %s -check-prefix=CHECK-GENERIC
3 ; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s -check-prefix=CHECK-UNALIGNED
|
| armv4.ll | 2 ; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
5 ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM
10 ; ARM: mov pc
|
| ctor_order.ll | 1 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
2 ; RUN: llc < %s -mtriple=arm-linux-gnu | FileCheck %s -check-prefix=ELF
3 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=GNUEABI
|
| ctors_dtors.ll | 1 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
2 ; RUN: llc < %s -mtriple=arm-linux-gnu | FileCheck %s -check-prefix=ELF
3 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=GNUEABI
|
| fast-isel-call-multi-reg-return.ll | 1 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
14 ; ARM: @t1
|
| fmscs.ll | 1 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
3 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
|
| fnmacs.ll | 1 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
3 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
|
| mls.ll | 1 ; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
2 ; RUN: llc < %s -march=arm -mattr=+v6t2 -arm-use-mulops=false | FileCheck %s -check-prefix=NO_MULOPS
|
| uxt_rot.ll | 1 ; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtb | count 1
2 ; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtab | count 1
3 ; RUN: llc < %s -march=arm -mattr=+v6 | grep uxth | count 1
|
| vcvt.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s
71 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
79 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
87 %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
95 %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
99 declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone
100 declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone
101 declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
102 declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
108 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1
[all...] |
| /external/oprofile/libop/ |
| op_cpu_type.c | 45 { "ARM/XScale PMU1", "arm/xscale1", CPU_ARM_XSCALE1, 3 },
46 { "ARM/XScale PMU2", "arm/xscale2", CPU_ARM_XSCALE2, 5 },
73 { "ARM 11MPCore", "arm/mpcore", CPU_ARM_MPCORE, 2 },
74 { "ARM V6 PMU", "arm/armv6", CPU_ARM_V6, 3 },
78 { "ARM Cortex-A8", "arm/armv7", CPU_ARM_V7, 5 }
[all...] |
| /external/qemu/ |
| translate.make | 14 OP_OBJ := $(INTERMEDIATE)/target-arm/op.o
31 TRANSLATE_SOURCES := target-arm/translate.c \
35 LOCAL_SRC_FILES += target-arm/op.c $(TRANSLATE_SOURCES)
|
| /ndk/tests/device/test-cpufeatures/jni/ |
| Android.mk | 21 ifeq ($(TARGET_ARCH),arm)
29 ifeq ($(TARGET_ARCH),arm)
37 LOCAL_ARM_MODE := arm
|
