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  /prebuilts/ndk/4/platforms/android-5/arch-arm/usr/lib/
libthread_db.so 
  /prebuilts/ndk/4/platforms/android-8/arch-arm/usr/lib/
libthread_db.so 
  /prebuilts/ndk/5/platforms/android-3/arch-arm/usr/lib/
libthread_db.so 
  /prebuilts/ndk/6/platforms/android-3/arch-arm/usr/lib/
libthread_db.so 
  /prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.7/lib/gcc/arm-linux-androideabi/4.7/
libgcc.a     [all...]
  /external/llvm/test/CodeGen/ARM/
spill-q.ll 10 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
21 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %vecptr, i32 1) nounwind ; <<4 x float>> [#uses=1]
23 %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
25 %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
26 %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
30 %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
32 %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
34 %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
36 %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwin
    [all...]
vqdmul.ll 10 %tmp3 = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
19 %tmp3 = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
28 %tmp3 = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
37 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
46 %1 = tail call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; <<8 x i16>> [#uses=1]
55 %1 = tail call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; <<4 x i32>> [#uses=1]
64 %1 = tail call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i16>> [#uses=1]
73 %1 = tail call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i32>> [#uses=1]
77 declare <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
78 declare <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnon
    [all...]
vcnt.ll 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
83 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
91 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
99 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
107 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
115 %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
123 %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
127 declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone
128 declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone
129 declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnon
    [all...]
reg_sequence.ll 1 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s
2 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s
27 %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
37 %15 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %13, <4 x i32> <i32 -12, i32 -12, i32 -12, i32 -12>) ; <<4 x i16>> [#uses=1]
38 %16 = tail call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %14, <4 x i32> <i32 -12, i32 -12, i32 -12, i32 -12>) ; <<4 x i16>> [#uses=1]
41 tail call void @llvm.arm.neon.vst1.v8i16(i8* %18, <8 x i16> %17, i32 1)
61 %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1]
64 %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %7, i32 1) ; <<8 x i16>> [#uses=1]
68 tail call void @llvm.arm.neon.vst1.v8i16(i8* %11, <8 x i16> %9, i32 1)
71 tail call void @llvm.arm.neon.vst1.v8i16(i8* %13, <8 x i16> %10, i32 1
    [all...]
  /external/llvm/test/CodeGen/Thumb2/
thumb2-spill-q.ll 10 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
21 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %vecptr, i32 1) nounwind
23 %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
25 %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
26 %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
30 %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
32 %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
34 %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
36 %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwin
    [all...]
  /external/qemu/distrib/sdl-1.2.15/
README.Qtopia 16 II. Building the Simple DirectMedia Layer libraries using the arm
25 NM=arm-linux-nm LD=arm-linux-ld CC=arm-linux-gcc CXX=arm-linux-g++ RANLIB=arm-linux-ranlib AR=arm-linux-ar ./configure --enable-video-qtopia --disable-video-dummy --disable-video-fbcon --disable-video-dga --disable-arts --disable-esd --disable-alsa --disable-cdrom --disable-video-x11 --disable-nasm --prefix=/opt/Qtopia/sharp/ arm-unknown-linux-gnu
38 NM=arm-linux-nm LD=arm-linux-ld CC=arm-linux-gcc CXX=arm-linux-g++ AR=arm-linux-ar ./configure arm-unknown-linux-gn
    [all...]
  /prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.7/lib/gcc/arm-linux-androideabi/4.7/armv7-a/
libgcc.a     [all...]
  /prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.7/lib/gcc/arm-linux-androideabi/4.7/thumb/
libgcc.a     [all...]
  /external/llvm/lib/Target/ARM/
A15SDOptimizer.cpp 12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
28 #include "ARM.h"
57 return "ARM A15 S->D optimizer";
152 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
153 &ARM::DPRRegClass);
154 if (DReg != ARM::NoRegister) return ARM::ssub_1;
155 return ARM::ssub_0;
165 if (!MI) return ARM::ssub_0;
169 if (!MO) return ARM::ssub_0
    [all...]
ARMJITInfo.cpp 1 //===-- ARMJITInfo.cpp - Implement the JIT interfaces for the ARM target --===//
10 // This file implements the JIT interfaces for the ARM target.
16 #include "ARM.h"
105 #else // Not an ARM host
107 llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!");
239 ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType();
243 case ARM::reloc_arm_pic_jt:
246 case ARM::reloc_arm_jt_base:
249 case ARM::reloc_arm_cp_entry
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ARM.td 1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
20 // ARM Subtarget state.
27 // ARM Subtarget features.
41 "Does not support ARM mode execution",
55 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
57 "Enable divide instructions in ARM mode">;
126 // ARM ISAs.
128 "Support ARM v4T instructions">;
130 "Support ARM v5T instructions"
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  /prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.7/lib/gcc/arm-linux-androideabi/4.7/armv7-a/thumb/
libgcc.a     [all...]
  /build/core/
dumpvar.mk 12 # Add the ARM toolchain bin dir if it actually exists
13 ifeq ($(TARGET_ARCH),arm)
14 ifneq ($(wildcard $(PWD)/prebuilts/gcc/$(HOST_PREBUILT_TAG)/arm/arm-linux-androideabi-$(TARGET_GCC_VERSION)/bin),)
16 ABP:=$(ABP):$(PWD)/prebuilts/gcc/$(HOST_PREBUILT_TAG)/arm/arm-linux-androideabi-$(TARGET_GCC_VERSION)/bin
18 ifneq ($(wildcard $(PWD)/prebuilts/gcc/$(HOST_PREBUILT_TAG)/arm/arm-eabi-$(TARGET_GCC_VERSION)/bin),)
20 ABP:=$(ABP):$(PWD)/prebuilts/gcc/$(HOST_PREBUILT_TAG)/arm/arm-eabi-$(TARGET_GCC_VERSION)/bi
    [all...]
  /external/llvm/test/Transforms/InstCombine/
2012-04-23-Neon-Intrinsics.ll 8 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
16 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
25 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
33 %b = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
41 %b = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
49 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
53 ; CHECK-NEXT: %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]]
59 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
67 declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
68 declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnon
    [all...]
  /ndk/docs/text/
CPU-ARM-NEON.text 1 Android NDK & ARM NEON instruction set extension support
6 Android NDK r3 added support for the new 'armeabi-v7a' ARM-based ABI
9 - Thumb-2, which provides performance comparable to 32-bit ARM
21 instruction set extension known as "ARM Advanced SIMD", nick-named
36 flag will be used to enable the use of GCC ARM Neon intrinsics and
39 > http://gcc.gnu.org/onlinedocs/gcc/ARM-NEON-Intrinsics.html
62 Note that the .neon suffix can be used with the .arm suffix too (used to
63 specify the 32-bit ARM instruction set for non-NEON instructions), but must
66 In other words, 'foo.c.arm.neon' works, but 'foo.c.neon.arm' does NOT
    [all...]
  /external/clang/test/CodeGen/
atomics-inlining.c 1 // RUN: %clang_cc1 -triple arm-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM
34 // ARM: define arm_aapcscc void @test1
35 // ARM: = call arm_aapcscc zeroext i8 @__atomic_load_1(i8* @c1
36 // ARM: call arm_aapcscc void @__atomic_store_1(i8* @c1, i8 zeroext
37 // ARM: = call arm_aapcscc zeroext i16 @__atomic_load_2(i8* bitcast (i16* @s1 to i8*)
38 // ARM: call arm_aapcscc void @__atomic_store_2(i8* bitcast (i16* @s1 to i8*), i16 zeroext
39 // ARM: = call arm_aapcscc i32 @__atomic_load_4(i8* bitcast (i32* @i1 to i8*)
40 // ARM: call arm_aapcscc void @__atomic_store_4(i8* bitcast (i32* @i1 to i8*), i32
41 // ARM: = call arm_aapcscc i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*
    [all...]
  /prebuilts/ndk/8/sources/cxx-stl/gabi++/libs/armeabi/
libgabi++_static.a 18   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`?K{Dh3`???? ??F????? ???? ??F????????vPvPKvbPbPKbwPwPKwDsPDsPKDsDiPDiPKDicPcPKcaPaPKahPhPKhsPsPKstPtPKtiPiPKijPjPKjlPlPKlmPmPKmxPxPKxyPyPKyfPfPKfdPdPKdePePKeDfPDfPKDfDdPDdPKDdDePDePKDeDnPDnPKDnN10__cxxabiv123__fundamental_type_infoEGCC: (GNU) 4.6 20120106 (prerelease)A,aeabi"5TE ,.symtab.strtab.shstrtab.rel.text.data.bss.ARM.extab.rel.ARM.exidx.rel.data.rel.ro._ZTIPKDn.rel.data.rel.ro._ZTIPDn.rel.data.rel.ro._ZTIDn.rel.data.rel.ro._ZTIPKDe.rel.data.rel.ro._ZTIPDe.rel.data.rel.ro._ZTIDe.rel.data.rel.ro._ZTIPKDd.rel.data.rel.ro._ZTIPDd.rel.data.rel.ro._ZTIDd.rel.data.rel.ro._ZTIPKDf.rel.data.rel.ro._ZTIPDf.rel.data.rel.ro._ZTIDf.rel.data.rel.ro._ZTIPKe.rel.data.rel.ro._ZTIPe.rel.data.rel.ro._ZTIe.rel.data.rel.ro._ZTIPKd.rel.data.rel.ro._ZTIPd.rel.data.rel.ro._ZTId.rel.data.rel.ro._ZTIPKf.rel.data.rel.ro._ZTIPf.rel.data.rel.ro._ZTIf.rel.data.rel.ro._ZTIPKy.rel.data.rel.ro._ZTIPy.rel.data.rel.ro._ZTIy.rel.data.rel.ro._ZTIPKx.rel.data.rel.ro._ZTIPx.rel.data.rel.ro._ZTIx.rel.data.rel.ro._ZTIPKm.rel.data.rel.ro._ZTIPm.rel.data.rel.ro._ZTIm.rel.data.rel.ro._ZTIPKl.rel.data.rel.ro._ZTIPl.rel.data.rel.ro._ZTIl.rel.data.rel.ro._ZTIPKj.rel.data.rel.ro._ZTIPj.rel.data.rel.ro._ZTIj.rel.data.rel.ro._ZTIPKi.rel.data.rel.ro._ZTIPi.rel.data.rel.ro._ZTIi.rel.data.rel.ro._ZTIPKt.rel.data.rel.ro._ZTIPt.rel.data.rel.ro._ZTIt.rel.data.rel.ro._ZTIPKs.rel.data.rel.ro._ZTIPs.rel.data.rel.ro._ZTIs.rel.data.rel.ro._ZTIPKh.rel.data.rel.ro._ZTIPh.rel.data.rel.ro._ZTIh.rel.data.rel.ro._ZTIPKa.rel.data.rel.ro._ZTIPa.rel.data.rel.ro._ZTIa.rel.data.rel.ro._ZTIPKc.rel.data.rel.ro._ZTIPc.rel.data.rel.ro._ZTIc.rel.data.rel.ro._ZTIPKDi.rel.data.rel.ro._ZTIPDi.rel.data.rel.ro._ZTIDi.rel.data.rel.ro._ZTIPKDs.rel.data.rel.ro._ZTIPDs.rel.data.rel.ro._ZTIDs.rel.data.rel.ro._ZTIPKw.rel.data.rel.ro._ZTIPw.rel.data.rel.ro._ZTIw.rel.data.rel.ro._ZTIPKb.rel.data.rel.ro._ZTIPb.rel.data.rel.ro._ZTIb.rel.data.rel.ro._ZTIPKv.rel.data.rel.ro._ZTIPv.rel.data.rel.ro._ZTIv.rodata._ZTSv.rodata._ZTSPv.rodata._ZTSPKv.rodata._ZTSb.rodata._ZTSPb.rodata._ZTSPKb.rodata._ZTSw.rodata._ZTSPw.rodata._ZTSPKw.rodata._ZTSDs.rodata._ZTSPDs.rodata._ZTSPKDs.rodata._ZTSDi.rodata._ZTSPDi.rodata._ZTSPKDi.rodata._ZTSc.rodata._ZTSPc.rodata._ZTSPKc.rodata._ZTSa.rodata._ZTSPa.rodata._ZTSPKa.rodata._ZTSh.rodata._ZTSPh.rodata._ZTSPKh.rodata._ZTSs.rodata._ZTSPs.rodata._ZTSPKs.rodata._ZTSt.rodata._ZTSPt.rodata._ZTSPKt.rodata._ZTSi.rodata._ZTSPi.rodata._ZTSPKi.rodata._ZTSj.rodata._ZTSPj.rodata._ZTSPKj.rodata._ZTSl.rodata._ZTSPl.rodata._ZTSPKl.rodata._ZTSm.rodata._ZTSPm.rodata._ZTSPKm.rodata._ZTSx.rodata._ZTSPx.rodata._ZTSPKx.rodata._ZTSy.rodata._ZTSPy.rodata._ZTSPKy.rodata._ZTSf.rodata._ZTSPf.rodata._ZTSPKf.rodata._ZTSd.rodata._ZTSPd.rodata._ZTSPKd.rodata._ZTSe.rodata._ZTSPe.rodata._ZTSPKe.rodata._ZTSDf.rodata._ZTSPDf.rodata._ZTSPKDf.rodata._ZTSDd.rodata._ZTSPDd.rodata._ZTSPKDd.rodata._ZTSDe.rodata._ZTSPDe.rodata._ZTSPKDe.rodata._ZTSDn.rodata._ZTSPDn.rodata._ZTSPKDn.rodata.rel.data.rel.ro.comment.note.GNU-stack.ARM.attributes.group3 4h?3 <h?3 Dh?3 Lh?3 Th?3 \h?3 dh?3 lh?3 th?3 |h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 h?3  h?3 h?3 h?3 $h?3 ,h?3 4h?3 <h?3 Dh?3 Lh?3 Th3 \h3 dh3 lh3 th 3 |h
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  /prebuilts/ndk/8/sources/cxx-stl/gabi++/libs/armeabi-v7a/
libgabi++_static.a 20 ,.symtab.strtab.shstrtab.rel.text.data.bss.ARM.extab.rel.ARM.exidx.rel.data.rel.ro._ZTIPKDn.rel.data.rel.ro._ZTIPDn.rel.data.rel.ro._ZTIDn.rel.data.rel.ro._ZTIPKDe.rel.data.rel.ro._ZTIPDe.rel.data.rel.ro._ZTIDe.rel.data.rel.ro._ZTIPKDd.rel.data.rel.ro._ZTIPDd.rel.data.rel.ro._ZTIDd.rel.data.rel.ro._ZTIPKDf.rel.data.rel.ro._ZTIPDf.rel.data.rel.ro._ZTIDf.rel.data.rel.ro._ZTIPKe.rel.data.rel.ro._ZTIPe.rel.data.rel.ro._ZTIe.rel.data.rel.ro._ZTIPKd.rel.data.rel.ro._ZTIPd.rel.data.rel.ro._ZTId.rel.data.rel.ro._ZTIPKf.rel.data.rel.ro._ZTIPf.rel.data.rel.ro._ZTIf.rel.data.rel.ro._ZTIPKy.rel.data.rel.ro._ZTIPy.rel.data.rel.ro._ZTIy.rel.data.rel.ro._ZTIPKx.rel.data.rel.ro._ZTIPx.rel.data.rel.ro._ZTIx.rel.data.rel.ro._ZTIPKm.rel.data.rel.ro._ZTIPm.rel.data.rel.ro._ZTIm.rel.data.rel.ro._ZTIPKl.rel.data.rel.ro._ZTIPl.rel.data.rel.ro._ZTIl.rel.data.rel.ro._ZTIPKj.rel.data.rel.ro._ZTIPj.rel.data.rel.ro._ZTIj.rel.data.rel.ro._ZTIPKi.rel.data.rel.ro._ZTIPi.rel.data.rel.ro._ZTIi.rel.data.rel.ro._ZTIPKt.rel.data.rel.ro._ZTIPt.rel.data.rel.ro._ZTIt.rel.data.rel.ro._ZTIPKs.rel.data.rel.ro._ZTIPs.rel.data.rel.ro._ZTIs.rel.data.rel.ro._ZTIPKh.rel.data.rel.ro._ZTIPh.rel.data.rel.ro._ZTIh.rel.data.rel.ro._ZTIPKa.rel.data.rel.ro._ZTIPa.rel.data.rel.ro._ZTIa.rel.data.rel.ro._ZTIPKc.rel.data.rel.ro._ZTIPc.rel.data.rel.ro._ZTIc.rel.data.rel.ro._ZTIPKDi.rel.data.rel.ro._ZTIPDi.rel.data.rel.ro._ZTIDi.rel.data.rel.ro._ZTIPKDs.rel.data.rel.ro._ZTIPDs.rel.data.rel.ro._ZTIDs.rel.data.rel.ro._ZTIPKw.rel.data.rel.ro._ZTIPw.rel.data.rel.ro._ZTIw.rel.data.rel.ro._ZTIPKb.rel.data.rel.ro._ZTIPb.rel.data.rel.ro._ZTIb.rel.data.rel.ro._ZTIPKv.rel.data.rel.ro._ZTIPv.rel.data.rel.ro._ZTIv.rodata._ZTSv.rodata._ZTSPv.rodata._ZTSPKv.rodata._ZTSb.rodata._ZTSPb.rodata._ZTSPKb.rodata._ZTSw.rodata._ZTSPw.rodata._ZTSPKw.rodata._ZTSDs.rodata._ZTSPDs.rodata._ZTSPKDs.rodata._ZTSDi.rodata._ZTSPDi.rodata._ZTSPKDi.rodata._ZTSc.rodata._ZTSPc.rodata._ZTSPKc.rodata._ZTSa.rodata._ZTSPa.rodata._ZTSPKa.rodata._ZTSh.rodata._ZTSPh.rodata._ZTSPKh.rodata._ZTSs.rodata._ZTSPs.rodata._ZTSPKs.rodata._ZTSt.rodata._ZTSPt.rodata._ZTSPKt.rodata._ZTSi.rodata._ZTSPi.rodata._ZTSPKi.rodata._ZTSj.rodata._ZTSPj.rodata._ZTSPKj.rodata._ZTSl.rodata._ZTSPl.rodata._ZTSPKl.rodata._ZTSm.rodata._ZTSPm.rodata._ZTSPKm.rodata._ZTSx.rodata._ZTSPx.rodata._ZTSPKx.rodata._ZTSy.rodata._ZTSPy.rodata._ZTSPKy.rodata._ZTSf.rodata._ZTSPf.rodata._ZTSPKf.rodata._ZTSd.rodata._ZTSPd.rodata._ZTSPKd.rodata._ZTSe.rodata._ZTSPe.rodata._ZTSPKe.rodata._ZTSDf.rodata._ZTSPDf.rodata._ZTSPKDf.rodata._ZTSDd.rodata._ZTSPDd.rodata._ZTSPKDd.rodata._ZTSDe.rodata._ZTSPDe.rodata._ZTSPKDe.rodata._ZTSDn.rodata._ZTSPDn.rodata._ZTSPKDn.rodata.rel.data.rel.ro.comment.note.GNU-stack.ARM.attributes.group3 4h?3 <h?3 Dh?3 Lh?3 Th?3 \h?3 dh?3 lh?3 th?3 |h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 ?h?3 h?3  h?3 h?3 h?3 $h?3 ,h?3 4h?3 <h?3 Dh?3 Lh?3 Th3 \h3 dh3 lh3 th 3 |h
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  /bionic/libc/kernel/tools/
defaults.py 10 kernel_archs = [ 'arm', 'x86', 'mips' ]
46 "arm": {},
52 "arm": {},
63 # in the final ARM headers. this is only used to keep optimized byteswapping
66 [ "___arch__swab32", # asm-arm/byteorder.h
94 "arm" : kernel_known_arm_statics,
  /external/chromium_org/v8/src/arm/
cpu-arm.cc 28 // CPU specific code for arm independent of OS goes here.
61 // Not generating ARM instructions for C-code. This means that we are
62 // building an ARM emulator based target. We should notify the simulator
88 "@ Enter ARM Mode \n\t"
92 ".ARM \n"
112 UNIMPLEMENTED(); // when building ARM emulator target

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