| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 116 SmallVectorImpl<MachineOperand> &Cond,
121 const SmallVectorImpl<MachineOperand> &Cond,
126 const SmallVectorImpl<MachineOperand> &Cond,
131 const SmallVectorImpl<MachineOperand> &Cond,
152 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
| PPCInstrInfo.cpp | 228 SmallVectorImpl<MachineOperand> &Cond,
260 Cond.push_back(LastInst->getOperand(0));
261 Cond.push_back(LastInst->getOperand(1));
270 Cond.push_back(MachineOperand::CreateImm(1));
271 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
281 Cond.push_back(MachineOperand::CreateImm(0));
282 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
306 Cond.push_back(SecondLastInst->getOperand(0));
307 Cond.push_back(SecondLastInst->getOperand(1));
319 Cond.push_back(MachineOperand::CreateImm(1))
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 129 /// setting TBB to the destination basic block and populating the Cond vector
134 SmallVectorImpl<MachineOperand> &Cond) {
143 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
144 Cond.push_back(I->getOperand(0));
152 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
153 Cond.push_back(I->getOperand(0));
154 Cond.push_back(I->getOperand(1));
166 SmallVectorImpl<MachineOperand> &Cond,
192 classifyCondBranch(LastInst, TBB, Cond);
228 Cond.push_back(MachineOperand::CreateImm(AArch64::Bcc))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.h | 66 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
69 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
|
| R600ISelLowering.cpp | 445 SDValue Cond = (isZero(LHS) ? RHS : LHS);
463 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
488 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC);
492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32,
493 DAG.getNode(ISD::FNEG, DL, VT, Cond));
496 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
501 SDValue Cond;
507 Cond = DAG.getNode(
515 Cond = DAG.getNode(
520 Cond);
[all...] |
| /external/clang/test/SemaTemplate/ |
| constructor-template.cpp | 60 X2 test(bool Cond, X2 x2) {
61 if (Cond)
80 X4 test_X4(bool Cond, X4 x4) {
|
| instantiate-expr-3.cpp | 80 template<bool Cond, typename T, typename U, typename Result>
83 Result r = __builtin_choose_expr(Cond, t, u); // expected-error{{lvalue}}
|
| instantiate-expr-2.cpp | 77 struct Cond {
81 enum { resultT = Cond<true>::is,
82 resultF = Cond<false>::is };
92 struct Cond {
97 typedef Cond<true, int, char>::True True;
98 typedef Cond<true, int, char>::False False;
112 struct Cond {
117 //Cond<true, int*, double> C; // Errors
119 //typedef Cond<true, int*, double>::Type Type; // Errors
120 typedef Cond<true, int, double>::Type Type
[all...] |
| overload-candidates.cpp | 52 template<typename Cond, typename T = void> struct enable_if : boost::enable_if<Cond::value, T> {};
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.h | 66 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
69 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
|
| R600ISelLowering.cpp | 445 SDValue Cond = (isZero(LHS) ? RHS : LHS);
463 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
488 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC);
492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32,
493 DAG.getNode(ISD::FNEG, DL, VT, Cond));
496 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
501 SDValue Cond;
507 Cond = DAG.getNode(
515 Cond = DAG.getNode(
520 Cond);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 314 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
[all...] |
| /external/clang/lib/Sema/ |
| ScopeInfo.cpp | 141 if (const ConditionalOperator *Cond = dyn_cast<ConditionalOperator>(E)) {
142 markSafeWeakUse(Cond->getTrueExpr());
143 markSafeWeakUse(Cond->getFalseExpr());
147 if (const BinaryConditionalOperator *Cond =
149 markSafeWeakUse(Cond->getCommon());
150 markSafeWeakUse(Cond->getFalseExpr());
|
| /external/chromium_org/content/common/ |
| sandbox_seccomp_bpf_linux.cc | 1307 return sandbox->Cond(3, ErrorCode::TP_32BIT, ErrorCode::OP_HAS_ANY_BITS,
1319 return sandbox->Cond(2, ErrorCode::TP_32BIT, ErrorCode::OP_HAS_ANY_BITS,
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIAnnotateControlFlow.cpp | 82 void handleLoopCondition(Value *Cond);
205 void SIAnnotateControlFlow::handleLoopCondition(Value *Cond) {
206 if (PHINode *Phi = dyn_cast<PHINode>(Cond)) {
248 } else if (Instruction *Inst = dyn_cast<Instruction>(Cond)) {
251 Value *Args[] = { Cond, PhiInserter.GetValueAtEndOfBlock(Parent) };
268 Value *Cond = Term->getCondition();
270 handleLoopCondition(Cond);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 116 llvm_unreachable("Invalid cond code");
122 SmallVectorImpl<MachineOperand> &Cond,
154 Cond.clear();
175 if (Cond.empty()) {
211 Cond.push_back(MachineOperand::CreateImm(BranchCode));
224 const SmallVectorImpl<MachineOperand> &Cond,
227 assert((Cond.size() == 1 || Cond.size() == 0) &&
230 if (Cond.empty()) {
237 unsigned CC = Cond[0].getImm()
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CorrelatedValuePropagation.cpp | 206 Value *Cond = SI->getCondition();
211 if (isa<Instruction>(Cond) && cast<Instruction>(Cond)->getParent() == BB)
231 Cond, Case, *PI, BB);
260 Cond = SI->getCondition();
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 141 SmallVectorImpl<MachineOperand> &Cond,
183 Cond.clear();
200 if (Cond.empty()) {
204 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
205 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
210 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
218 unsigned OldCCValid = Cond[0].getImm();
219 unsigned OldCCMask = Cond[1].getImm();
253 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
254 assert(Cond.size() == 2 && "Invalid condition")
[all...] |
| SystemZInstrInfo.h | 125 SmallVectorImpl<MachineOperand> &Cond,
130 const SmallVectorImpl<MachineOperand> &Cond,
180 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
190 // When returning true, set Cond to the mask of condition-code
|
| /external/clang/test/SemaCXX/ |
| conditional-expr.cpp | 238 void f(bool Cond, String S, OtherString OS) {
239 (void)(Cond? S : "");
240 (void)(Cond? "" : S);
242 (void)(Cond? S : a);
243 (void)(Cond? a : S);
244 (void)(Cond? OS : S);
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 272 SmallVectorImpl<MachineOperand> &Cond,
296 const SmallVectorImpl<MachineOperand> &Cond,
372 /// condition code in Cond.
375 /// FalseReg, and Cond to the destination register. In most cases, a select
381 /// @param Cond Condition returned by AnalyzeBranch.
382 /// @param TrueReg Virtual register to select when Cond is true.
383 /// @param FalseReg Virtual register to select when Cond is false.
384 /// @param CondCycles Latency from Cond+Branch to select output.
388 const SmallVectorImpl<MachineOperand> &Cond,
396 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg whe
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 119 const SmallVectorImpl<MachineOperand> &Cond,
131 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
137 if (Cond.empty()) {
143 SmallVector<MachineOperand, 4> Cond;
145 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
150 ReverseBranchCondition(Cond);
152 return InsertBranch(MBB, TBB, 0, Cond, DL);
158 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB)
[all...] |
| HexagonInstrInfo.h | 61 SmallVectorImpl<MachineOperand> &Cond,
68 const SmallVectorImpl<MachineOperand> &Cond,
120 const SmallVectorImpl<MachineOperand> &Cond) const;
145 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
| /external/llvm/lib/IR/ |
| ConstantFold.h | 35 Constant *ConstantFoldSelectInstruction(Constant *Cond,
|
