| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 138 const ARMSubtarget *STI;
250 if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
638 STI->avoidMOVsShifterOperand())
755 STI->avoidMOVsShifterOperand())
[all...] |
| Thumb2InstrInfo.cpp | 33 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
34 : ARMBaseInstrInfo(STI), RI(STI) {
|
| Thumb1FrameLowering.cpp | 139 if (STI.isTargetIOS()) {
188 if (STI.isTargetELF() && HasFP)
|
| ARMBaseInstrInfo.h | 35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
|
| ARMLoadStoreOptimizer.cpp | 67 const ARMSubtarget *STI;
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterInlineAsm.cpp | 122 STI(TM.getTarget().createMCSubtargetInfo(TM.getTargetTriple(),
126 TAP(TM.getTarget().createMCAsmParser(*STI, *Parser));
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 42 const MCSubtargetInfo &STI) :
45 setAvailableFeatures(STI.getFeatureBits());
|
| AArch64InstPrinter.h | 29 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 302 const MCSubtargetInfo &STI) {
|
| HexagonFrameLowering.cpp | 168 if (STI.hasV4TOps() && MBBI->getOpcode() == Hexagon::JMPret
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCTargetDesc.cpp | 123 const MCSubtargetInfo &STI) {
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCTargetDesc.cpp | 154 const MCSubtargetInfo &STI) {
|
| /external/llvm/tools/llvm-objdump/ |
| llvm-objdump.cpp | 289 OwningPtr<const MCSubtargetInfo> STI(
291 if (!STI) {
302 OwningPtr<MCDisassembler> DisAsm(TheTarget->createMCDisassembler(*STI));
329 AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 93 ARMDisassembler(const MCSubtargetInfo &STI) :
94 MCDisassembler(STI) {
114 ThumbDisassembler(const MCSubtargetInfo &STI) :
115 MCDisassembler(STI) {
409 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
410 return new ARMDisassembler(STI);
413 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
414 return new ThumbDisassembler(STI);
426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
443 Address, this, STI);
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 41 const MCSubtargetInfo &STI;
45 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
47 : MCII(mcii), STI(sti), CTX(ctx) {
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
60 Triple TT(STI.getTargetTriple());
344 const MCSubtargetInfo &STI,
346 return new ARMMCCodeEmitter(MCII, STI, Ctx);
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 35 const MCSubtargetInfo &STI;
38 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
40 : MCII(mcii), STI(sti), Ctx(ctx) {
47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
52 return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
152 const MCSubtargetInfo &STI,
154 return new X86MCCodeEmitter(MCII, STI, Ctx);
[all...] |
| X86MCTargetDesc.cpp | 379 const MCSubtargetInfo &STI) {
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.h | 27 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 295 MCSubtargetInfo &STI;
330 SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
331 : MCTargetAsmParser(), STI(sti), Parser(parser) {
335 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 63 MCSubtargetInfo &STI;
168 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
172 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
200 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
201 : MCTargetAsmParser(), STI(sti), Parser(parser) {
203 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 485 const MCSubtargetInfo &STI,
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 175 MCSubtargetInfo &STI;
222 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
224 Triple TheTriple(STI.getTargetTriple());
228 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 37 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
39 Subtarget(STI) {}
|
| /external/llvm/tools/lto/ |
| LTOModule.cpp | 816 STI(T.createMCSubtargetInfo(_target->getTargetTriple(),
819 OwningPtr<MCTargetAsmParser> TAP(T.createMCAsmParser(*STI, *Parser.get()));
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 49 MCSubtargetInfo &STI;
538 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
541 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
558 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
559 : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
562 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
[all...] |
