| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 37 const TargetSubtargetInfo *STI;
44 TargetSchedModel(): STI(0), TII(0) {}
51 void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
107 return STI->getWriteProcResBegin(SC);
110 return STI->getWriteProcResEnd(SC);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.h | 29 PPCFrameLowering(const PPCSubtarget &sti)
31 (sti.hasQPX() || sti.isBGQ()) ? 32 : 16, 0),
32 Subtarget(sti) {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.h | 26 const SystemZSubtarget &STI;
30 const SystemZSubtarget &sti);
|
| SystemZFrameLowering.cpp | 48 const SystemZSubtarget &sti)
51 TM(tm), STI(sti) {
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 38 const MCSubtargetInfo &STI;
43 const MCSubtargetInfo &sti)
44 : MCII(mcii), MRI(mri), STI(sti) { }
86 const MCSubtargetInfo &STI) {
87 return new R600MCCodeEmitter(MCII, MRI, STI);
102 if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) {
135 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
|
| SIMCCodeEmitter.cpp | 51 const MCSubtargetInfo &sti, MCContext &ctx)
69 const MCSubtargetInfo &STI,
71 return new SIMCCodeEmitter(MCII, MRI, STI, Ctx);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 63 const MCSubtargetInfo &STI;
67 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
69 : MCII(mcii), STI(sti), Ctx(ctx) { }
126 const MCSubtargetInfo &STI,
128 return new SIMCCodeEmitter(MCII, STI, Ctx);
|
| R600MCCodeEmitter.cpp | 43 const MCSubtargetInfo &STI;
48 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
50 : MCII(mcii), STI(sti), Ctx(ctx) { }
145 const MCSubtargetInfo &STI,
147 return new R600MCCodeEmitter(MCII, STI, Ctx);
|
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 55 const TargetSubtargetInfo *sti,
58 STI = sti;
60 STI->initInstrItins(InstrItins);
117 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
193 STI->getWriteLatencyEntry(SCDesc, DefIdx);
204 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
241 STI->getWriteLatencyEntry(SCDesc, DefIdx);
276 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
277 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 63 const MCSubtargetInfo &STI;
67 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
69 : MCII(mcii), STI(sti), Ctx(ctx) { }
126 const MCSubtargetInfo &STI,
128 return new SIMCCodeEmitter(MCII, STI, Ctx);
|
| R600MCCodeEmitter.cpp | 43 const MCSubtargetInfo &STI;
48 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
50 : MCII(mcii), STI(sti), Ctx(ctx) { }
145 const MCSubtargetInfo &STI,
147 return new R600MCCodeEmitter(MCII, STI, Ctx);
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 35 const MCSubtargetInfo &STI;
40 PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
42 : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) {
104 const MCSubtargetInfo &STI,
106 return new PPCMCCodeEmitter(MCII, STI, Ctx);
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 40 const MCSubtargetInfo &STI;
45 const MCSubtargetInfo &sti, bool IsLittle) :
46 MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {}
102 const MCSubtargetInfo &STI,
105 return new MipsMCCodeEmitter(MCII, Ctx, STI, false);
110 const MCSubtargetInfo &STI,
113 return new MipsMCCodeEmitter(MCII, Ctx, STI, true);
213 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
|
| /external/grub/stage1/ |
| stage1.S | 140 sti /* we're safe again */
|
| /external/grub/stage2/ |
| start_eltorito.S | 89 sti
|
| asm.S | 135 sti /* we're safe again */
933 sti
[all...] |
| /external/kernel-headers/original/linux/ |
| interrupt.h | 182 static inline void __deprecated sti(void) function
366 * 2. sti();
|
| /external/qemu/target-i386/ |
| helper.h | 69 DEF_HELPER_0(sti, void)
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 46 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti)
47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti),
48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
66 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
75 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
97 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()
[all...] |
| Thumb1RegisterInfo.cpp | 43 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMSubtarget &sti)
44 : ARMBaseRegisterInfo(sti) {
|
| /external/qemu-pc-bios/bochs/bios/ |
| apmbios.S | 228 sti
|
| rombios.c | 2921 sti ;; enable higher priority interrupts local
3072 sti ;; enable higher priority interrupts local
3224 sti ;; enable higher priority interrupts local
4491 sti local
6455 sti ;; enable higher priority interrupts local
6595 sti ;; enable higher priority interrupts local
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 80 XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti)
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 295 MCSubtargetInfo &STI;
330 SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
331 : MCTargetAsmParser(), STI(sti), Parser(parser) {
335 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 41 const MCSubtargetInfo &STI;
45 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
47 : MCII(mcii), STI(sti), CTX(ctx) {
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
60 Triple TT(STI.getTargetTriple());
344 const MCSubtargetInfo &STI,
346 return new ARMMCCodeEmitter(MCII, STI, Ctx);
[all...] |
