/external/llvm/test/CodeGen/AArch64/ |
zero-reg.ll | 23 ; instruction (0b11111 in the Rn field would mean "sp").
|
/external/llvm/lib/Target/XCore/ |
XCoreInstrFormats.td | 56 let Inst{15-11} = 0b11111; 85 let Inst{15-11} = 0b11111; 209 let Inst{15-11} = 0b11111; 245 let Inst{15-11} = 0b11111; 266 let Inst{15-11} = 0b11111; 274 let Inst{15-11} = 0b11111;
|
/external/llvm/lib/Target/ARM/ |
ARMInstrThumb2.td | 871 let Inst{31-27} = 0b11111; [all...] |
ARMInstrFormats.td | [all...] |
/external/arduino/hardware/arduino/cores/arduino/ |
binary.h | 158 #define B11111 31
|
/external/llvm/lib/Target/Mips/ |
MipsDSPInstrInfo.td | 124 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>; 145 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>; 206 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>; 246 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>; [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.td | 445 let Rd = 0b11111, isCompare = 1 in { 669 let Rd = 0b11111; [all...] |
AArch64InstrNEON.td | 295 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv, 537 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps", 543 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", [all...] |
AArch64InstrFormats.td | 497 let Inst{28-24} = 0b11111;
|
/art/runtime/ |
dex_file.h | [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
brw_blorp_blit.cpp | 418 * | (Y' & 0b11111) << 4 [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
X86MCCodeEmitter.cpp | 575 // 0b00100-0b11111: Reserved for future use [all...] |
/external/llvm/lib/Target/X86/ |
X86CodeEmitter.cpp | 851 // 0b00100-0b11111: Reserved for future use [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
brw_blorp_blit.cpp | 418 * | (Y' & 0b11111) << 4 [all...] |
/external/llvm/test/MC/Disassembler/AArch64/ |
basic-a64-instructions.txt | 1086 # First check some non-canonical encodings where Ra is not 0b11111 (only umulh [all...] |