| /external/llvm/lib/Target/X86/ |
| X86InstrFormats.td | 167 InstrItinClass itin,
184 let Itinerary = itin;
255 list<dag> pattern, InstrItinClass itin = NoItinerary,
257 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
262 list<dag> pattern, InstrItinClass itin = NoItinerary,
264 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
269 list<dag> pattern, InstrItinClass itin = NoItinerary>
270 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
275 list<dag> pattern, InstrItinClass itin = NoItinerary>
276 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrFormats.td | 14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
25 let Itinerary = itin;
67 InstrItinClass itin>
79 let Itinerary = itin;
100 InstrItinClass itin, list<dag> pattern>
101 : I<opcode, OOL, IOL, asmstr, itin> {
164 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
166 : I<opcode, OOL, IOL, asmstr, itin> {
177 InstrItinClass itin, list<dag> pattern>
178 : I<opcode, OOL, IOL, asmstr, itin> {
[all...] |
| PPCInstrInfo.td | 588 string asmbase, string asmstr, InstrItinClass itin,
592 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
596 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
602 string asmbase, string asmstr, InstrItinClass itin,
607 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
611 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
617 string asmbase, string asmstr, InstrItinClass itin,
621 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
625 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
631 string asmbase, string asmstr, InstrItinClass itin,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrFormats.td | 257 Format f, Domain d, string cstr, InstrItinClass itin>
288 let Itinerary = itin;
304 Format f, Domain d, string cstr, InstrItinClass itin>
305 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
312 Format f, Domain d, string cstr, InstrItinClass itin>
313 : InstTemplate<am, sz, im, f, d, cstr, itin> {
343 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
345 GenericDomain, "", itin> {
354 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
356 : PseudoInst<oops, iops, itin, pattern>
[all...] |
| ARMInstrNEON.td | 581 class VLDQPseudo<InstrItinClass itin>
582 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
583 class VLDQWBPseudo<InstrItinClass itin>
585 (ins addrmode6:$addr, am6offset:$offset), itin,
587 class VLDQWBfixedPseudo<InstrItinClass itin>
589 (ins addrmode6:$addr), itin,
591 class VLDQWBregisterPseudo<InstrItinClass itin>
593 (ins addrmode6:$addr, rGPR:$offset), itin,
596 class VLDQQPseudo<InstrItinClass itin>
597 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
[all...] |
| ARMInstrThumb2.td | 293 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
295 : T2I<oops, iops, itin, opc, asm, pattern> {
306 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
308 : T2sI<oops, iops, itin, opc, asm, pattern> {
319 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
321 : T2I<oops, iops, itin, opc, asm, pattern> {
332 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
334 : T2I<oops, iops, itin, opc, asm, pattern> {
345 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
347 : T2sI<oops, iops, itin, opc, asm, pattern>
[all...] |
| ARMInstrThumb.td | 771 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
773 : T1pI<oops, iops, itin, opc, asm, pattern>,
780 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
782 : T1pI<oops, iops, itin, opc, asm, pattern>,
791 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
793 : T1sI<oops, iops, itin, opc, asm, pattern>,
800 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
802 : T1sI<oops, iops, itin, opc, asm, pattern>,
811 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
813 : T1sI<oops, iops, itin, opc, asm, pattern>
[all...] |
| ARMInstrVFP.td | 127 InstrItinClass itin, InstrItinClass itin_upd> {
131 IndexModeNone, itin,
159 IndexModeNone, itin,
875 InstrItinClass itin, string opc, string asm,
877 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
891 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
893 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrFormats.td | 21 InstrItinClass itin>
42 let Itinerary = itin;
72 list<dag> patterns, InstrItinClass itin>
73 : A64Inst<outs, ins, asmstr, patterns, itin> {
80 list<dag> patterns, InstrItinClass itin>
81 : A64Inst<outs, ins, asmstr, patterns, itin> {
89 list<dag> patterns, InstrItinClass itin>
90 : A64InstRd<outs, ins, asmstr, patterns, itin> {
98 list<dag> patterns, InstrItinClass itin>
99 : A64InstRt<outs, ins, asmstr, patterns, itin> {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrFormats.td | 37 InstrItinClass itin>: Instruction
47 let Itinerary = itin;
56 InstrItinClass itin>:
57 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
73 InstrItinClass itin>:
74 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
83 InstrItinClass itin>:
84 MipsInst16_32<outs, ins, asmstr, pattern, itin>
104 InstrItinClass itin>:
105 MipsInst16<outs, ins, asmstr, pattern, itin>
[all...] |
| Mips16InstrInfo.td | 40 string asmstr2, InstrItinClass itin>:
42 [], itin>;
46 InstrItinClass itin>:
47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
55 InstrItinClass itin>:
57 !strconcat(asmstr, asmstr2), [], itin>;
60 InstrItinClass itin>:
61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
64 InstrItinClass itin>:
66 !strconcat(asmstr, asmstr2), [], itin>;
[all...] |
| MipsDSPInstrInfo.td | 259 InstrItinClass itin, RegisterClass RCD,
265 InstrItinClass Itinerary = itin;
269 InstrItinClass itin, RegisterClass RCD,
275 InstrItinClass Itinerary = itin;
279 InstrItinClass itin, RegisterClass RCS,
285 InstrItinClass Itinerary = itin;
289 InstrItinClass itin, RegisterClass RCD,
295 InstrItinClass Itinerary = itin;
299 InstrItinClass itin, RegisterClass RCT,
305 InstrItinClass Itinerary = itin;
[all...] |
| MipsInstrFPU.td | 92 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
96 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
100 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
102 def _D32 : ADDS_FT<opstr, AFGR64RegsOpnd, Itin, IsComm, OpNode>,
104 def _D64 : ADDS_FT<opstr, FGR64RegsOpnd, Itin, IsComm, OpNode>,
111 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
113 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
116 multiclass ABSS_M<string opstr, InstrItinClass Itin,
118 def _D32 : ABSS_FT<opstr, AFGR64RegsOpnd, AFGR64RegsOpnd, Itin, OpNode>,
120 def _D64 : ABSS_FT<opstr, FGR64RegsOpnd, FGR64RegsOpnd, Itin, OpNode>
[all...] |
| MipsCondMov.td | 20 InstrItinClass Itin> :
22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR> {
28 InstrItinClass Itin> :
30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> {
35 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
40 Itin, FrmFR> {
45 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
50 Itin, FrmFR> {
|
| MipsInstrFormats.td | 59 InstrItinClass itin, Format f>: Instruction
78 let Itinerary = itin;
95 InstrItinClass itin, Format f, string opstr = ""> :
96 MipsInst<outs, ins, asmstr, pattern, itin, f> {
104 InstrItinClass itin = IIPseudo> :
105 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
112 InstrItinClass itin = IIPseudo>:
113 MipsPseudo<outs, ins, pattern, itin> {
130 list<dag> pattern, InstrItinClass itin>:
131 InstSE<outs, ins, asmstr, pattern, itin, FrmR
[all...] |
| MipsInstrInfo.td | 382 InstrItinClass Itin = NoItinerary,
386 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
393 InstrItinClass Itin = NoItinerary,
399 Itin, FrmI, opstr> {
444 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
453 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
464 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
475 InstrItinClass Itin = NoItinerary,
477 def NAME : Load<opstr, OpNode, RO, Itin, mem, Addr, "">,
479 def _P8 : Load<opstr, OpNode, RO, Itin, mem64, Addr, "_p8">
[all...] |
| MipsDSPInstrFormats.td | 28 InstrItinClass itin = IIPseudo>:
29 MipsPseudo<outs, ins, pattern, itin> {
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| Processors.td | 14 class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
15 : Processor<Name, itin, Features>;
|
| R600Instructions.td | 17 InstrItinClass itin>
32 let Itinerary = itin;
79 InstrItinClass itin = AnyALU> :
85 itin
89 InstrItinClass itin = AnyALU> :
95 itin
99 InstrItinClass itin = AnyALU> :
105 itin>{
135 InstrItinClass itin = VecALU> :
141 itin
[all...] |
| /external/llvm/lib/Target/R600/ |
| Processors.td | 10 class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
11 : Processor<Name, itin, Features>;
|
| R600InstrFormats.td | 15 InstrItinClass itin>
38 let Itinerary = itin;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| Processors.td | 14 class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
15 : Processor<Name, itin, Features>;
|
| R600Instructions.td | 17 InstrItinClass itin>
32 let Itinerary = itin;
79 InstrItinClass itin = AnyALU> :
85 itin
89 InstrItinClass itin = AnyALU> :
95 itin
99 InstrItinClass itin = AnyALU> :
105 itin>{
135 InstrItinClass itin = VecALU> :
141 itin
[all...] |
| /packages/apps/Exchange/res/values-fr/ |
| strings.xml | 54 <string name="policy_require_manual_sync_roaming" msgid="6637416341015662148">"Interdire synchro auto en itinérance"</string>
|
| /packages/apps/Exchange/res/values-fr-rCA/ |
| strings.xml | 54 <string name="policy_require_manual_sync_roaming" msgid="6637416341015662148">"Interdire synchro auto en itinérance"</string>
|
