| /external/llvm/test/CodeGen/AArch64/ |
| regress-f128csel-flags.ll | 3 ; We used to not mark NZCV as being used in the continuation basic-block
21 ; function call since bl may corrupt NZCV. We were doing the right thing anyway,
|
| flags-multiuse.ll | 26 ; acceptable, but assuming the call preserves NZCV is not.
|
| /external/valgrind/main/none/tests/arm/ |
| v6intThumb.stdout.exp | 350 uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
351 uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV
359 sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
360 sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV
368 uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
369 uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
377 sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
378 sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.td | 196 def NZCV : Register<"nzcv"> {
200 def FlagClass : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
|
| AArch64InstrInfo.td | 36 // (ins NZCV, Condition, Dest)
40 // (outs Result), (ins NZCV, IfTrue, IfFalse, Condition)
46 // (outs NZCV), (ins LHS, RHS, Condition)
206 let Defs = [NZCV] in {
222 let Defs = [NZCV];
407 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>;
426 let Defs = [NZCV] in {
657 let Defs = [NZCV];
666 [(set NZCV,
670 let Defs = [NZCV];
[all...] |
| AArch64InstrInfo.cpp | 59 } else if (DestReg == AArch64::NZCV) {
61 // E.g. MSR NZCV, xDST
63 .addImm(A64SysReg::NZCV)
65 } else if (SrcReg == AArch64::NZCV) {
67 // E.g. MRS xDST, NZCV
69 .addImm(A64SysReg::NZCV);
|
| AArch64ISelLowering.cpp | 676 EndBB->addLiveIn(AArch64::NZCV);
[all...] |
| /external/valgrind/main/VEX/priv/ |
| guest_arm_defs.h | 78 /* Calculate NZCV from the supplied thunk components, in the positions
129 details of the most recent flag-setting operation, so NZCV can
170 ARMG_CC_OP_COPY=0, /* DEP1 = NZCV in 31:28, DEP2 = 0, DEP3 = 0
|
| guest_arm_helpers.c | 119 /* (nzcv:28x0, unused, unused) */
199 /* (nzcv:28x0, unused, unused) */
280 /* (nzcv:28x0, unused, unused) */
361 /* (nzcv:28x0, unused, unused) */
433 /* Calculate NZCV from the supplied thunk components, in the positions
915 // NZCV
[all...] |
| guest_arm_toIR.c | 2506 IRTemp nzcv = newTemp(Ity_I32); local
11676 IRTemp nzcv = IRTemp_INVALID; local
12144 IRTemp nzcv = IRTemp_INVALID; local
[all...] |
| host_arm_defs.h | 646 /* CMP/TST; subtract/and, discard result, set NZCV */
|
| host_arm_isel.c | 53 exceptions masked, round-to-nearest, non-vector mode, with the NZCV
[all...] |
| /external/valgrind/main/coregrind/m_dispatch/ |
| dispatch-arm-linux.S | 98 bic r4, #0xF8000000 /* mask out NZCV and QC */
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 394 {"nzcv", NZCV},
[all...] |
| AArch64BaseInfo.h | 545 NZCV = 0xda10, // 11 011 0100 0010 000
[all...] |
| /external/llvm/test/MC/AArch64/ |
| basic-a64-instructions.s | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| basic-a64-instructions.txt | [all...] |
| /external/qemu/target-arm/ |
| translate.c | 211 /* Set NZCV flags from the high 4 bits of var. */
[all...] |
