| /external/llvm/test/CodeGen/ARM/ |
| 2012-09-25-InlineAsmScalarToVectorConv.ll | 7 %1 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } asm "vldm $4, { ${0:q}, ${1:q}, ${2:q}, ${3:q} }", "=r,=r,=r,=r,r"(i64* undef) nounwind, !srcloc !0
|
| /external/clang/test/CodeGen/ |
| arm-asm-warn.c | 25 __asm__("vldm %[a], { %q[r0], %q[r1], %q[r2], %q[r3] }"
|
| arm-asm-diag.c | 11 __asm__("vldm %[a], { %q[r0], %q[r1], %q[r2], %q[r3] }"
|
| /external/v8/test/cctest/ |
| test-assembler-arm.cc | 641 // Create a function that uses vldm/vstm to move some double and
653 __ vldm(ia_w, r4, d0, d3);
654 __ vldm(ia_w, r4, d4, d7);
661 __ vldm(ia_w, r4, s0, s3);
662 __ vldm(ia_w, r4, s4, s7);
752 // Create a function that uses vldm/vstm to move some double and
764 __ vldm(ia, r4, d0, d3);
766 __ vldm(ia, r4, d4, d7);
774 __ vldm(ia, r4, s0, s3);
776 __ vldm(ia, r4, s4, s7)
[all...] |
| test-disasm-arm.cc | 528 COMPARE(vldm(ia, r1, d2, d5),
532 COMPARE(vldm(ia, r3, d0, d15),
536 COMPARE(vldm(ia, r5, s2, s5),
540 COMPARE(vldm(ia, r7, s0, s31),
|
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-arm.cc | 653 // Create a function that uses vldm/vstm to move some double and
662 __ vldm(ia_w, r4, d0, d3);
663 __ vldm(ia_w, r4, d4, d7);
670 __ vldm(ia_w, r4, s0, s3);
671 __ vldm(ia_w, r4, s4, s7);
761 // Create a function that uses vldm/vstm to move some double and
770 __ vldm(ia, r4, d0, d3);
772 __ vldm(ia, r4, d4, d7);
780 __ vldm(ia, r4, s0, s3);
782 __ vldm(ia, r4, s4, s7)
[all...] |
| test-disasm-arm.cc | 558 COMPARE(vldm(ia, r1, d2, d5),
562 COMPARE(vldm(ia, r3, d0, d15),
566 COMPARE(vldm(ia, r5, s2, s5),
570 COMPARE(vldm(ia, r7, s0, s31),
658 COMPARE(vldm(ia, r3, d16, d31),
662 COMPARE(vldm(ia, r3, d23, d27),
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMScheduleA9.td | [all...] |
| ARMBaseInstrInfo.h | 239 /// Get the number of addresses by LDM or VLDM or zero for unknown.
|
| ARMLoadStoreOptimizer.cpp | 47 STATISTIC(NumVLDMGened, "Number of vldm instructions generated");
303 // VLDM/VSTM do not support DB mode without also updating the base reg.
463 // vldm / vstm limit are 32 for S variants, 16 for D variants.
699 /// register into the LDM/STM/VLDM{D|S}/VSTM{D|S} op when possible:
925 // VLDM[SD}_UPD, VSTM[SD]_UPD
[all...] |
| ARMScheduleSwift.td | [all...] |
| ARMInstrVFP.td | 200 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
207 def : MnemonicAlias<"vldm", "vldmia">;
[all...] |
| README.txt | 309 5) Use VLDM / VSTM to emulate indexed FP load / store.
|
| /art/runtime/ |
| disassembler_arm.cc | 509 if (op3 == 9 || op3 == 0xD) { // VLDM
528 } else { // VLDM
529 opcode << "vldm" << (S == 0 ? ".f64" : ".f32");
[all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | [all...] |
| disasm-arm.cc | [all...] |
| assembler-arm.cc | [all...] |
| /art/compiler/dex/quick/ |
| gen_invoke.cc | 747 * Pass args 3-18 using vldm/vstm block copy
[all...] |
| /external/chromium_org/v8/src/arm/ |
| assembler-arm.h | [all...] |
| disasm-arm.cc | [all...] |
| macro-assembler-arm.cc | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | [all...] |
| /external/libyuv/files/source/ |
| row_neon.cc | 366 "vldm %0!, {q0, q1, q2, q3} \n" // load 64
[all...] |
| /art/runtime/arch/arm/ |
| quick_entrypoints_arm.S | 296 vldm r1, {s0-s31} @ load all fprs from argument fprs_
[all...] |
| /external/llvm/test/MC/ARM/ |
| neon-vld-encoding.s | 492 @ Register lists can use the range syntax, just like VLDM
|
