1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 2 // All Rights Reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are 6 // met: 7 // 8 // - Redistributions of source code must retain the above copyright notice, 9 // this list of conditions and the following disclaimer. 10 // 11 // - Redistribution in binary form must reproduce the above copyright 12 // notice, this list of conditions and the following disclaimer in the 13 // documentation and/or other materials provided with the distribution. 14 // 15 // - Neither the name of Sun Microsystems or the names of contributors may 16 // be used to endorse or promote products derived from this software without 17 // specific prior written permission. 18 // 19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31 // The original source code covered by the above license above has been 32 // modified significantly by Google Inc. 33 // Copyright 2012 the V8 project authors. All rights reserved. 34 35 // A lightweight X64 Assembler. 36 37 #ifndef V8_X64_ASSEMBLER_X64_H_ 38 #define V8_X64_ASSEMBLER_X64_H_ 39 40 #include "serialize.h" 41 42 namespace v8 { 43 namespace internal { 44 45 // Utility functions 46 47 // Test whether a 64-bit value is in a specific range. 48 inline bool is_uint32(int64_t x) { 49 static const uint64_t kMaxUInt32 = V8_UINT64_C(0xffffffff); 50 return static_cast<uint64_t>(x) <= kMaxUInt32; 51 } 52 53 inline bool is_int32(int64_t x) { 54 static const int64_t kMinInt32 = -V8_INT64_C(0x80000000); 55 return is_uint32(x - kMinInt32); 56 } 57 58 inline bool uint_is_int32(uint64_t x) { 59 static const uint64_t kMaxInt32 = V8_UINT64_C(0x7fffffff); 60 return x <= kMaxInt32; 61 } 62 63 inline bool is_uint32(uint64_t x) { 64 static const uint64_t kMaxUInt32 = V8_UINT64_C(0xffffffff); 65 return x <= kMaxUInt32; 66 } 67 68 // CPU Registers. 69 // 70 // 1) We would prefer to use an enum, but enum values are assignment- 71 // compatible with int, which has caused code-generation bugs. 72 // 73 // 2) We would prefer to use a class instead of a struct but we don't like 74 // the register initialization to depend on the particular initialization 75 // order (which appears to be different on OS X, Linux, and Windows for the 76 // installed versions of C++ we tried). Using a struct permits C-style 77 // "initialization". Also, the Register objects cannot be const as this 78 // forces initialization stubs in MSVC, making us dependent on initialization 79 // order. 80 // 81 // 3) By not using an enum, we are possibly preventing the compiler from 82 // doing certain constant folds, which may significantly reduce the 83 // code generated for some assembly instructions (because they boil down 84 // to a few constants). If this is a problem, we could change the code 85 // such that we use an enum in optimized mode, and the struct in debug 86 // mode. This way we get the compile-time error checking in debug mode 87 // and best performance in optimized code. 88 // 89 90 struct Register { 91 // The non-allocatable registers are: 92 // rsp - stack pointer 93 // rbp - frame pointer 94 // rsi - context register 95 // r10 - fixed scratch register 96 // r12 - smi constant register 97 // r13 - root register 98 static const int kMaxNumAllocatableRegisters = 10; 99 static int NumAllocatableRegisters() { 100 return kMaxNumAllocatableRegisters; 101 } 102 static const int kNumRegisters = 16; 103 104 static int ToAllocationIndex(Register reg) { 105 return kAllocationIndexByRegisterCode[reg.code()]; 106 } 107 108 static Register FromAllocationIndex(int index) { 109 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 110 Register result = { kRegisterCodeByAllocationIndex[index] }; 111 return result; 112 } 113 114 static const char* AllocationIndexToString(int index) { 115 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 116 const char* const names[] = { 117 "rax", 118 "rbx", 119 "rdx", 120 "rcx", 121 "rdi", 122 "r8", 123 "r9", 124 "r11", 125 "r14", 126 "r15" 127 }; 128 return names[index]; 129 } 130 131 static Register from_code(int code) { 132 Register r = { code }; 133 return r; 134 } 135 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; } 136 bool is(Register reg) const { return code_ == reg.code_; } 137 // rax, rbx, rcx and rdx are byte registers, the rest are not. 138 bool is_byte_register() const { return code_ <= 3; } 139 int code() const { 140 ASSERT(is_valid()); 141 return code_; 142 } 143 int bit() const { 144 return 1 << code_; 145 } 146 147 // Return the high bit of the register code as a 0 or 1. Used often 148 // when constructing the REX prefix byte. 149 int high_bit() const { 150 return code_ >> 3; 151 } 152 // Return the 3 low bits of the register code. Used when encoding registers 153 // in modR/M, SIB, and opcode bytes. 154 int low_bits() const { 155 return code_ & 0x7; 156 } 157 158 // Unfortunately we can't make this private in a struct when initializing 159 // by assignment. 160 int code_; 161 162 private: 163 static const int kRegisterCodeByAllocationIndex[kMaxNumAllocatableRegisters]; 164 static const int kAllocationIndexByRegisterCode[kNumRegisters]; 165 }; 166 167 const int kRegister_rax_Code = 0; 168 const int kRegister_rcx_Code = 1; 169 const int kRegister_rdx_Code = 2; 170 const int kRegister_rbx_Code = 3; 171 const int kRegister_rsp_Code = 4; 172 const int kRegister_rbp_Code = 5; 173 const int kRegister_rsi_Code = 6; 174 const int kRegister_rdi_Code = 7; 175 const int kRegister_r8_Code = 8; 176 const int kRegister_r9_Code = 9; 177 const int kRegister_r10_Code = 10; 178 const int kRegister_r11_Code = 11; 179 const int kRegister_r12_Code = 12; 180 const int kRegister_r13_Code = 13; 181 const int kRegister_r14_Code = 14; 182 const int kRegister_r15_Code = 15; 183 const int kRegister_no_reg_Code = -1; 184 185 const Register rax = { kRegister_rax_Code }; 186 const Register rcx = { kRegister_rcx_Code }; 187 const Register rdx = { kRegister_rdx_Code }; 188 const Register rbx = { kRegister_rbx_Code }; 189 const Register rsp = { kRegister_rsp_Code }; 190 const Register rbp = { kRegister_rbp_Code }; 191 const Register rsi = { kRegister_rsi_Code }; 192 const Register rdi = { kRegister_rdi_Code }; 193 const Register r8 = { kRegister_r8_Code }; 194 const Register r9 = { kRegister_r9_Code }; 195 const Register r10 = { kRegister_r10_Code }; 196 const Register r11 = { kRegister_r11_Code }; 197 const Register r12 = { kRegister_r12_Code }; 198 const Register r13 = { kRegister_r13_Code }; 199 const Register r14 = { kRegister_r14_Code }; 200 const Register r15 = { kRegister_r15_Code }; 201 const Register no_reg = { kRegister_no_reg_Code }; 202 203 #ifdef _WIN64 204 // Windows calling convention 205 const Register arg_reg_1 = { kRegister_rcx_Code }; 206 const Register arg_reg_2 = { kRegister_rdx_Code }; 207 const Register arg_reg_3 = { kRegister_r8_Code }; 208 const Register arg_reg_4 = { kRegister_r9_Code }; 209 #else 210 // AMD64 calling convention 211 const Register arg_reg_1 = { kRegister_rdi_Code }; 212 const Register arg_reg_2 = { kRegister_rsi_Code }; 213 const Register arg_reg_3 = { kRegister_rdx_Code }; 214 const Register arg_reg_4 = { kRegister_rcx_Code }; 215 #endif // _WIN64 216 217 struct XMMRegister { 218 static const int kMaxNumRegisters = 16; 219 static const int kMaxNumAllocatableRegisters = 15; 220 static int NumAllocatableRegisters() { 221 return kMaxNumAllocatableRegisters; 222 } 223 224 static int ToAllocationIndex(XMMRegister reg) { 225 ASSERT(reg.code() != 0); 226 return reg.code() - 1; 227 } 228 229 static XMMRegister FromAllocationIndex(int index) { 230 ASSERT(0 <= index && index < kMaxNumAllocatableRegisters); 231 XMMRegister result = { index + 1 }; 232 return result; 233 } 234 235 static const char* AllocationIndexToString(int index) { 236 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 237 const char* const names[] = { 238 "xmm1", 239 "xmm2", 240 "xmm3", 241 "xmm4", 242 "xmm5", 243 "xmm6", 244 "xmm7", 245 "xmm8", 246 "xmm9", 247 "xmm10", 248 "xmm11", 249 "xmm12", 250 "xmm13", 251 "xmm14", 252 "xmm15" 253 }; 254 return names[index]; 255 } 256 257 static XMMRegister from_code(int code) { 258 ASSERT(code >= 0); 259 ASSERT(code < kMaxNumRegisters); 260 XMMRegister r = { code }; 261 return r; 262 } 263 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters; } 264 bool is(XMMRegister reg) const { return code_ == reg.code_; } 265 int code() const { 266 ASSERT(is_valid()); 267 return code_; 268 } 269 270 // Return the high bit of the register code as a 0 or 1. Used often 271 // when constructing the REX prefix byte. 272 int high_bit() const { 273 return code_ >> 3; 274 } 275 // Return the 3 low bits of the register code. Used when encoding registers 276 // in modR/M, SIB, and opcode bytes. 277 int low_bits() const { 278 return code_ & 0x7; 279 } 280 281 int code_; 282 }; 283 284 const XMMRegister xmm0 = { 0 }; 285 const XMMRegister xmm1 = { 1 }; 286 const XMMRegister xmm2 = { 2 }; 287 const XMMRegister xmm3 = { 3 }; 288 const XMMRegister xmm4 = { 4 }; 289 const XMMRegister xmm5 = { 5 }; 290 const XMMRegister xmm6 = { 6 }; 291 const XMMRegister xmm7 = { 7 }; 292 const XMMRegister xmm8 = { 8 }; 293 const XMMRegister xmm9 = { 9 }; 294 const XMMRegister xmm10 = { 10 }; 295 const XMMRegister xmm11 = { 11 }; 296 const XMMRegister xmm12 = { 12 }; 297 const XMMRegister xmm13 = { 13 }; 298 const XMMRegister xmm14 = { 14 }; 299 const XMMRegister xmm15 = { 15 }; 300 301 302 typedef XMMRegister DoubleRegister; 303 304 305 enum Condition { 306 // any value < 0 is considered no_condition 307 no_condition = -1, 308 309 overflow = 0, 310 no_overflow = 1, 311 below = 2, 312 above_equal = 3, 313 equal = 4, 314 not_equal = 5, 315 below_equal = 6, 316 above = 7, 317 negative = 8, 318 positive = 9, 319 parity_even = 10, 320 parity_odd = 11, 321 less = 12, 322 greater_equal = 13, 323 less_equal = 14, 324 greater = 15, 325 326 // Fake conditions that are handled by the 327 // opcodes using them. 328 always = 16, 329 never = 17, 330 // aliases 331 carry = below, 332 not_carry = above_equal, 333 zero = equal, 334 not_zero = not_equal, 335 sign = negative, 336 not_sign = positive, 337 last_condition = greater 338 }; 339 340 341 // Returns the equivalent of !cc. 342 // Negation of the default no_condition (-1) results in a non-default 343 // no_condition value (-2). As long as tests for no_condition check 344 // for condition < 0, this will work as expected. 345 inline Condition NegateCondition(Condition cc) { 346 return static_cast<Condition>(cc ^ 1); 347 } 348 349 350 // Corresponds to transposing the operands of a comparison. 351 inline Condition ReverseCondition(Condition cc) { 352 switch (cc) { 353 case below: 354 return above; 355 case above: 356 return below; 357 case above_equal: 358 return below_equal; 359 case below_equal: 360 return above_equal; 361 case less: 362 return greater; 363 case greater: 364 return less; 365 case greater_equal: 366 return less_equal; 367 case less_equal: 368 return greater_equal; 369 default: 370 return cc; 371 }; 372 } 373 374 375 // ----------------------------------------------------------------------------- 376 // Machine instruction Immediates 377 378 class Immediate BASE_EMBEDDED { 379 public: 380 explicit Immediate(int32_t value) : value_(value) {} 381 382 private: 383 int32_t value_; 384 385 friend class Assembler; 386 }; 387 388 389 // ----------------------------------------------------------------------------- 390 // Machine instruction Operands 391 392 enum ScaleFactor { 393 times_1 = 0, 394 times_2 = 1, 395 times_4 = 2, 396 times_8 = 3, 397 times_int_size = times_4, 398 times_pointer_size = times_8 399 }; 400 401 402 class Operand BASE_EMBEDDED { 403 public: 404 // [base + disp/r] 405 Operand(Register base, int32_t disp); 406 407 // [base + index*scale + disp/r] 408 Operand(Register base, 409 Register index, 410 ScaleFactor scale, 411 int32_t disp); 412 413 // [index*scale + disp/r] 414 Operand(Register index, 415 ScaleFactor scale, 416 int32_t disp); 417 418 // Offset from existing memory operand. 419 // Offset is added to existing displacement as 32-bit signed values and 420 // this must not overflow. 421 Operand(const Operand& base, int32_t offset); 422 423 // Checks whether either base or index register is the given register. 424 // Does not check the "reg" part of the Operand. 425 bool AddressUsesRegister(Register reg) const; 426 427 // Queries related to the size of the generated instruction. 428 // Whether the generated instruction will have a REX prefix. 429 bool requires_rex() const { return rex_ != 0; } 430 // Size of the ModR/M, SIB and displacement parts of the generated 431 // instruction. 432 int operand_size() const { return len_; } 433 434 private: 435 byte rex_; 436 byte buf_[6]; 437 // The number of bytes of buf_ in use. 438 byte len_; 439 440 // Set the ModR/M byte without an encoded 'reg' register. The 441 // register is encoded later as part of the emit_operand operation. 442 // set_modrm can be called before or after set_sib and set_disp*. 443 inline void set_modrm(int mod, Register rm); 444 445 // Set the SIB byte if one is needed. Sets the length to 2 rather than 1. 446 inline void set_sib(ScaleFactor scale, Register index, Register base); 447 448 // Adds operand displacement fields (offsets added to the memory address). 449 // Needs to be called after set_sib, not before it. 450 inline void set_disp8(int disp); 451 inline void set_disp32(int disp); 452 453 friend class Assembler; 454 }; 455 456 457 // CpuFeatures keeps track of which features are supported by the target CPU. 458 // Supported features must be enabled by a CpuFeatureScope before use. 459 // Example: 460 // if (assembler->IsSupported(SSE3)) { 461 // CpuFeatureScope fscope(assembler, SSE3); 462 // // Generate SSE3 floating point code. 463 // } else { 464 // // Generate standard SSE2 floating point code. 465 // } 466 class CpuFeatures : public AllStatic { 467 public: 468 // Detect features of the target CPU. Set safe defaults if the serializer 469 // is enabled (snapshots must be portable). 470 static void Probe(); 471 472 // Check whether a feature is supported by the target CPU. 473 static bool IsSupported(CpuFeature f) { 474 ASSERT(initialized_); 475 if (f == SSE3 && !FLAG_enable_sse3) return false; 476 if (f == SSE4_1 && !FLAG_enable_sse4_1) return false; 477 if (f == CMOV && !FLAG_enable_cmov) return false; 478 if (f == RDTSC && !FLAG_enable_rdtsc) return false; 479 if (f == SAHF && !FLAG_enable_sahf) return false; 480 return (supported_ & (static_cast<uint64_t>(1) << f)) != 0; 481 } 482 483 static bool IsFoundByRuntimeProbingOnly(CpuFeature f) { 484 ASSERT(initialized_); 485 return (found_by_runtime_probing_only_ & 486 (static_cast<uint64_t>(1) << f)) != 0; 487 } 488 489 static bool IsSafeForSnapshot(CpuFeature f) { 490 return (IsSupported(f) && 491 (!Serializer::enabled() || !IsFoundByRuntimeProbingOnly(f))); 492 } 493 494 private: 495 // Safe defaults include CMOV for X64. It is always available, if 496 // anyone checks, but they shouldn't need to check. 497 // The required user mode extensions in X64 are (from AMD64 ABI Table A.1): 498 // fpu, tsc, cx8, cmov, mmx, sse, sse2, fxsr, syscall 499 static const uint64_t kDefaultCpuFeatures = (1 << CMOV); 500 501 #ifdef DEBUG 502 static bool initialized_; 503 #endif 504 static uint64_t supported_; 505 static uint64_t found_by_runtime_probing_only_; 506 507 friend class ExternalReference; 508 DISALLOW_COPY_AND_ASSIGN(CpuFeatures); 509 }; 510 511 512 class Assembler : public AssemblerBase { 513 private: 514 // We check before assembling an instruction that there is sufficient 515 // space to write an instruction and its relocation information. 516 // The relocation writer's position must be kGap bytes above the end of 517 // the generated instructions. This leaves enough space for the 518 // longest possible x64 instruction, 15 bytes, and the longest possible 519 // relocation information encoding, RelocInfoWriter::kMaxLength == 16. 520 // (There is a 15 byte limit on x64 instruction length that rules out some 521 // otherwise valid instructions.) 522 // This allows for a single, fast space check per instruction. 523 static const int kGap = 32; 524 525 public: 526 // Create an assembler. Instructions and relocation information are emitted 527 // into a buffer, with the instructions starting from the beginning and the 528 // relocation information starting from the end of the buffer. See CodeDesc 529 // for a detailed comment on the layout (globals.h). 530 // 531 // If the provided buffer is NULL, the assembler allocates and grows its own 532 // buffer, and buffer_size determines the initial buffer size. The buffer is 533 // owned by the assembler and deallocated upon destruction of the assembler. 534 // 535 // If the provided buffer is not NULL, the assembler uses the provided buffer 536 // for code generation and assumes its size to be buffer_size. If the buffer 537 // is too small, a fatal error occurs. No deallocation of the buffer is done 538 // upon destruction of the assembler. 539 Assembler(Isolate* isolate, void* buffer, int buffer_size); 540 virtual ~Assembler() { } 541 542 // GetCode emits any pending (non-emitted) code and fills the descriptor 543 // desc. GetCode() is idempotent; it returns the same result if no other 544 // Assembler functions are invoked in between GetCode() calls. 545 void GetCode(CodeDesc* desc); 546 547 // Read/Modify the code target in the relative branch/call instruction at pc. 548 // On the x64 architecture, we use relative jumps with a 32-bit displacement 549 // to jump to other Code objects in the Code space in the heap. 550 // Jumps to C functions are done indirectly through a 64-bit register holding 551 // the absolute address of the target. 552 // These functions convert between absolute Addresses of Code objects and 553 // the relative displacements stored in the code. 554 static inline Address target_address_at(Address pc); 555 static inline void set_target_address_at(Address pc, Address target); 556 557 // Return the code target address at a call site from the return address 558 // of that call in the instruction stream. 559 static inline Address target_address_from_return_address(Address pc); 560 561 // This sets the branch destination (which is in the instruction on x64). 562 // This is for calls and branches within generated code. 563 inline static void deserialization_set_special_target_at( 564 Address instruction_payload, Address target) { 565 set_target_address_at(instruction_payload, target); 566 } 567 568 // This sets the branch destination (which is a load instruction on x64). 569 // This is for calls and branches to runtime code. 570 inline static void set_external_target_at(Address instruction_payload, 571 Address target) { 572 *reinterpret_cast<Address*>(instruction_payload) = target; 573 } 574 575 inline Handle<Object> code_target_object_handle_at(Address pc); 576 inline Address runtime_entry_at(Address pc); 577 // Number of bytes taken up by the branch target in the code. 578 static const int kSpecialTargetSize = 4; // Use 32-bit displacement. 579 // Distance between the address of the code target in the call instruction 580 // and the return address pushed on the stack. 581 static const int kCallTargetAddressOffset = 4; // Use 32-bit displacement. 582 // The length of call(kScratchRegister). 583 static const int kCallScratchRegisterInstructionLength = 3; 584 // The length of call(Immediate32). 585 static const int kShortCallInstructionLength = 5; 586 // The length of movq(kScratchRegister, address). 587 static const int kMoveAddressIntoScratchRegisterInstructionLength = 588 2 + kPointerSize; 589 // The length of movq(kScratchRegister, address) and call(kScratchRegister). 590 static const int kCallSequenceLength = 591 kMoveAddressIntoScratchRegisterInstructionLength + 592 kCallScratchRegisterInstructionLength; 593 594 // The js return and debug break slot must be able to contain an indirect 595 // call sequence, some x64 JS code is padded with int3 to make it large 596 // enough to hold an instruction when the debugger patches it. 597 static const int kJSReturnSequenceLength = kCallSequenceLength; 598 static const int kDebugBreakSlotLength = kCallSequenceLength; 599 static const int kPatchDebugBreakSlotReturnOffset = kCallTargetAddressOffset; 600 // Distance between the start of the JS return sequence and where the 601 // 32-bit displacement of a short call would be. The short call is from 602 // SetDebugBreakAtIC from debug-x64.cc. 603 static const int kPatchReturnSequenceAddressOffset = 604 kJSReturnSequenceLength - kPatchDebugBreakSlotReturnOffset; 605 // Distance between the start of the JS return sequence and where the 606 // 32-bit displacement of a short call would be. The short call is from 607 // SetDebugBreakAtIC from debug-x64.cc. 608 static const int kPatchDebugBreakSlotAddressOffset = 609 kDebugBreakSlotLength - kPatchDebugBreakSlotReturnOffset; 610 static const int kRealPatchReturnSequenceAddressOffset = 611 kMoveAddressIntoScratchRegisterInstructionLength - kPointerSize; 612 613 // One byte opcode for test eax,0xXXXXXXXX. 614 static const byte kTestEaxByte = 0xA9; 615 // One byte opcode for test al, 0xXX. 616 static const byte kTestAlByte = 0xA8; 617 // One byte opcode for nop. 618 static const byte kNopByte = 0x90; 619 620 // One byte prefix for a short conditional jump. 621 static const byte kJccShortPrefix = 0x70; 622 static const byte kJncShortOpcode = kJccShortPrefix | not_carry; 623 static const byte kJcShortOpcode = kJccShortPrefix | carry; 624 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero; 625 static const byte kJzShortOpcode = kJccShortPrefix | zero; 626 627 628 // --------------------------------------------------------------------------- 629 // Code generation 630 // 631 // Function names correspond one-to-one to x64 instruction mnemonics. 632 // Unless specified otherwise, instructions operate on 64-bit operands. 633 // 634 // If we need versions of an assembly instruction that operate on different 635 // width arguments, we add a single-letter suffix specifying the width. 636 // This is done for the following instructions: mov, cmp, inc, dec, 637 // add, sub, and test. 638 // There are no versions of these instructions without the suffix. 639 // - Instructions on 8-bit (byte) operands/registers have a trailing 'b'. 640 // - Instructions on 16-bit (word) operands/registers have a trailing 'w'. 641 // - Instructions on 32-bit (doubleword) operands/registers use 'l'. 642 // - Instructions on 64-bit (quadword) operands/registers use 'q'. 643 // 644 // Some mnemonics, such as "and", are the same as C++ keywords. 645 // Naming conflicts with C++ keywords are resolved by adding a trailing '_'. 646 647 // Insert the smallest number of nop instructions 648 // possible to align the pc offset to a multiple 649 // of m, where m must be a power of 2. 650 void Align(int m); 651 void Nop(int bytes = 1); 652 // Aligns code to something that's optimal for a jump target for the platform. 653 void CodeTargetAlign(); 654 655 // Stack 656 void pushfq(); 657 void popfq(); 658 659 void push(Immediate value); 660 // Push a 32 bit integer, and guarantee that it is actually pushed as a 661 // 32 bit value, the normal push will optimize the 8 bit case. 662 void push_imm32(int32_t imm32); 663 void push(Register src); 664 void push(const Operand& src); 665 666 void pop(Register dst); 667 void pop(const Operand& dst); 668 669 void enter(Immediate size); 670 void leave(); 671 672 // Moves 673 void movb(Register dst, const Operand& src); 674 void movb(Register dst, Immediate imm); 675 void movb(const Operand& dst, Register src); 676 677 // Move the low 16 bits of a 64-bit register value to a 16-bit 678 // memory location. 679 void movw(const Operand& dst, Register src); 680 681 void movl(Register dst, Register src); 682 void movl(Register dst, const Operand& src); 683 void movl(const Operand& dst, Register src); 684 void movl(const Operand& dst, Immediate imm); 685 // Load a 32-bit immediate value, zero-extended to 64 bits. 686 void movl(Register dst, Immediate imm32); 687 688 // Move 64 bit register value to 64-bit memory location. 689 void movq(const Operand& dst, Register src); 690 // Move 64 bit memory location to 64-bit register value. 691 void movq(Register dst, const Operand& src); 692 void movq(Register dst, Register src); 693 // Sign extends immediate 32-bit value to 64 bits. 694 void movq(Register dst, Immediate x); 695 // Move the offset of the label location relative to the current 696 // position (after the move) to the destination. 697 void movl(const Operand& dst, Label* src); 698 699 // Move sign extended immediate to memory location. 700 void movq(const Operand& dst, Immediate value); 701 // Instructions to load a 64-bit immediate into a register. 702 // All 64-bit immediates must have a relocation mode. 703 void movq(Register dst, void* ptr, RelocInfo::Mode rmode); 704 void movq(Register dst, int64_t value, RelocInfo::Mode rmode); 705 void movq(Register dst, const char* s, RelocInfo::Mode rmode); 706 // Moves the address of the external reference into the register. 707 void movq(Register dst, ExternalReference ext); 708 void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode); 709 710 void movsxbq(Register dst, const Operand& src); 711 void movsxwq(Register dst, const Operand& src); 712 void movsxlq(Register dst, Register src); 713 void movsxlq(Register dst, const Operand& src); 714 void movzxbq(Register dst, const Operand& src); 715 void movzxbl(Register dst, const Operand& src); 716 void movzxwq(Register dst, const Operand& src); 717 void movzxwl(Register dst, const Operand& src); 718 void movzxwl(Register dst, Register src); 719 720 // Repeated moves. 721 722 void repmovsb(); 723 void repmovsw(); 724 void repmovsl(); 725 void repmovsq(); 726 727 // Instruction to load from an immediate 64-bit pointer into RAX. 728 void load_rax(void* ptr, RelocInfo::Mode rmode); 729 void load_rax(ExternalReference ext); 730 731 // Conditional moves. 732 void cmovq(Condition cc, Register dst, Register src); 733 void cmovq(Condition cc, Register dst, const Operand& src); 734 void cmovl(Condition cc, Register dst, Register src); 735 void cmovl(Condition cc, Register dst, const Operand& src); 736 737 // Exchange two registers 738 void xchg(Register dst, Register src); 739 740 // Arithmetics 741 void addl(Register dst, Register src) { 742 arithmetic_op_32(0x03, dst, src); 743 } 744 745 void addl(Register dst, Immediate src) { 746 immediate_arithmetic_op_32(0x0, dst, src); 747 } 748 749 void addl(Register dst, const Operand& src) { 750 arithmetic_op_32(0x03, dst, src); 751 } 752 753 void addl(const Operand& dst, Immediate src) { 754 immediate_arithmetic_op_32(0x0, dst, src); 755 } 756 757 void addl(const Operand& dst, Register src) { 758 arithmetic_op_32(0x01, src, dst); 759 } 760 761 void addq(Register dst, Register src) { 762 arithmetic_op(0x03, dst, src); 763 } 764 765 void addq(Register dst, const Operand& src) { 766 arithmetic_op(0x03, dst, src); 767 } 768 769 void addq(const Operand& dst, Register src) { 770 arithmetic_op(0x01, src, dst); 771 } 772 773 void addq(Register dst, Immediate src) { 774 immediate_arithmetic_op(0x0, dst, src); 775 } 776 777 void addq(const Operand& dst, Immediate src) { 778 immediate_arithmetic_op(0x0, dst, src); 779 } 780 781 void sbbl(Register dst, Register src) { 782 arithmetic_op_32(0x1b, dst, src); 783 } 784 785 void sbbq(Register dst, Register src) { 786 arithmetic_op(0x1b, dst, src); 787 } 788 789 void cmpb(Register dst, Immediate src) { 790 immediate_arithmetic_op_8(0x7, dst, src); 791 } 792 793 void cmpb_al(Immediate src); 794 795 void cmpb(Register dst, Register src) { 796 arithmetic_op(0x3A, dst, src); 797 } 798 799 void cmpb(Register dst, const Operand& src) { 800 arithmetic_op(0x3A, dst, src); 801 } 802 803 void cmpb(const Operand& dst, Register src) { 804 arithmetic_op(0x38, src, dst); 805 } 806 807 void cmpb(const Operand& dst, Immediate src) { 808 immediate_arithmetic_op_8(0x7, dst, src); 809 } 810 811 void cmpw(const Operand& dst, Immediate src) { 812 immediate_arithmetic_op_16(0x7, dst, src); 813 } 814 815 void cmpw(Register dst, Immediate src) { 816 immediate_arithmetic_op_16(0x7, dst, src); 817 } 818 819 void cmpw(Register dst, const Operand& src) { 820 arithmetic_op_16(0x3B, dst, src); 821 } 822 823 void cmpw(Register dst, Register src) { 824 arithmetic_op_16(0x3B, dst, src); 825 } 826 827 void cmpw(const Operand& dst, Register src) { 828 arithmetic_op_16(0x39, src, dst); 829 } 830 831 void cmpl(Register dst, Register src) { 832 arithmetic_op_32(0x3B, dst, src); 833 } 834 835 void cmpl(Register dst, const Operand& src) { 836 arithmetic_op_32(0x3B, dst, src); 837 } 838 839 void cmpl(const Operand& dst, Register src) { 840 arithmetic_op_32(0x39, src, dst); 841 } 842 843 void cmpl(Register dst, Immediate src) { 844 immediate_arithmetic_op_32(0x7, dst, src); 845 } 846 847 void cmpl(const Operand& dst, Immediate src) { 848 immediate_arithmetic_op_32(0x7, dst, src); 849 } 850 851 void cmpq(Register dst, Register src) { 852 arithmetic_op(0x3B, dst, src); 853 } 854 855 void cmpq(Register dst, const Operand& src) { 856 arithmetic_op(0x3B, dst, src); 857 } 858 859 void cmpq(const Operand& dst, Register src) { 860 arithmetic_op(0x39, src, dst); 861 } 862 863 void cmpq(Register dst, Immediate src) { 864 immediate_arithmetic_op(0x7, dst, src); 865 } 866 867 void cmpq(const Operand& dst, Immediate src) { 868 immediate_arithmetic_op(0x7, dst, src); 869 } 870 871 void and_(Register dst, Register src) { 872 arithmetic_op(0x23, dst, src); 873 } 874 875 void and_(Register dst, const Operand& src) { 876 arithmetic_op(0x23, dst, src); 877 } 878 879 void and_(const Operand& dst, Register src) { 880 arithmetic_op(0x21, src, dst); 881 } 882 883 void and_(Register dst, Immediate src) { 884 immediate_arithmetic_op(0x4, dst, src); 885 } 886 887 void and_(const Operand& dst, Immediate src) { 888 immediate_arithmetic_op(0x4, dst, src); 889 } 890 891 void andl(Register dst, Immediate src) { 892 immediate_arithmetic_op_32(0x4, dst, src); 893 } 894 895 void andl(Register dst, Register src) { 896 arithmetic_op_32(0x23, dst, src); 897 } 898 899 void andl(Register dst, const Operand& src) { 900 arithmetic_op_32(0x23, dst, src); 901 } 902 903 void andb(Register dst, Immediate src) { 904 immediate_arithmetic_op_8(0x4, dst, src); 905 } 906 907 void decq(Register dst); 908 void decq(const Operand& dst); 909 void decl(Register dst); 910 void decl(const Operand& dst); 911 void decb(Register dst); 912 void decb(const Operand& dst); 913 914 // Sign-extends rax into rdx:rax. 915 void cqo(); 916 // Sign-extends eax into edx:eax. 917 void cdq(); 918 919 // Divide rdx:rax by src. Quotient in rax, remainder in rdx. 920 void idivq(Register src); 921 // Divide edx:eax by lower 32 bits of src. Quotient in eax, rem. in edx. 922 void idivl(Register src); 923 924 // Signed multiply instructions. 925 void imul(Register src); // rdx:rax = rax * src. 926 void imul(Register dst, Register src); // dst = dst * src. 927 void imul(Register dst, const Operand& src); // dst = dst * src. 928 void imul(Register dst, Register src, Immediate imm); // dst = src * imm. 929 // Signed 32-bit multiply instructions. 930 void imull(Register dst, Register src); // dst = dst * src. 931 void imull(Register dst, const Operand& src); // dst = dst * src. 932 void imull(Register dst, Register src, Immediate imm); // dst = src * imm. 933 934 void incq(Register dst); 935 void incq(const Operand& dst); 936 void incl(Register dst); 937 void incl(const Operand& dst); 938 939 void lea(Register dst, const Operand& src); 940 void leal(Register dst, const Operand& src); 941 942 // Multiply rax by src, put the result in rdx:rax. 943 void mul(Register src); 944 945 void neg(Register dst); 946 void neg(const Operand& dst); 947 void negl(Register dst); 948 949 void not_(Register dst); 950 void not_(const Operand& dst); 951 void notl(Register dst); 952 953 void or_(Register dst, Register src) { 954 arithmetic_op(0x0B, dst, src); 955 } 956 957 void orl(Register dst, Register src) { 958 arithmetic_op_32(0x0B, dst, src); 959 } 960 961 void or_(Register dst, const Operand& src) { 962 arithmetic_op(0x0B, dst, src); 963 } 964 965 void orl(Register dst, const Operand& src) { 966 arithmetic_op_32(0x0B, dst, src); 967 } 968 969 void or_(const Operand& dst, Register src) { 970 arithmetic_op(0x09, src, dst); 971 } 972 973 void or_(Register dst, Immediate src) { 974 immediate_arithmetic_op(0x1, dst, src); 975 } 976 977 void orl(Register dst, Immediate src) { 978 immediate_arithmetic_op_32(0x1, dst, src); 979 } 980 981 void or_(const Operand& dst, Immediate src) { 982 immediate_arithmetic_op(0x1, dst, src); 983 } 984 985 void orl(const Operand& dst, Immediate src) { 986 immediate_arithmetic_op_32(0x1, dst, src); 987 } 988 989 990 void rcl(Register dst, Immediate imm8) { 991 shift(dst, imm8, 0x2); 992 } 993 994 void rol(Register dst, Immediate imm8) { 995 shift(dst, imm8, 0x0); 996 } 997 998 void rcr(Register dst, Immediate imm8) { 999 shift(dst, imm8, 0x3); 1000 } 1001 1002 void ror(Register dst, Immediate imm8) { 1003 shift(dst, imm8, 0x1); 1004 } 1005 1006 void rorl(Register dst, Immediate imm8) { 1007 shift_32(dst, imm8, 0x1); 1008 } 1009 1010 void rorl_cl(Register dst) { 1011 shift_32(dst, 0x1); 1012 } 1013 1014 // Shifts dst:src left by cl bits, affecting only dst. 1015 void shld(Register dst, Register src); 1016 1017 // Shifts src:dst right by cl bits, affecting only dst. 1018 void shrd(Register dst, Register src); 1019 1020 // Shifts dst right, duplicating sign bit, by shift_amount bits. 1021 // Shifting by 1 is handled efficiently. 1022 void sar(Register dst, Immediate shift_amount) { 1023 shift(dst, shift_amount, 0x7); 1024 } 1025 1026 // Shifts dst right, duplicating sign bit, by shift_amount bits. 1027 // Shifting by 1 is handled efficiently. 1028 void sarl(Register dst, Immediate shift_amount) { 1029 shift_32(dst, shift_amount, 0x7); 1030 } 1031 1032 // Shifts dst right, duplicating sign bit, by cl % 64 bits. 1033 void sar_cl(Register dst) { 1034 shift(dst, 0x7); 1035 } 1036 1037 // Shifts dst right, duplicating sign bit, by cl % 64 bits. 1038 void sarl_cl(Register dst) { 1039 shift_32(dst, 0x7); 1040 } 1041 1042 void shl(Register dst, Immediate shift_amount) { 1043 shift(dst, shift_amount, 0x4); 1044 } 1045 1046 void shl_cl(Register dst) { 1047 shift(dst, 0x4); 1048 } 1049 1050 void shll_cl(Register dst) { 1051 shift_32(dst, 0x4); 1052 } 1053 1054 void shll(Register dst, Immediate shift_amount) { 1055 shift_32(dst, shift_amount, 0x4); 1056 } 1057 1058 void shr(Register dst, Immediate shift_amount) { 1059 shift(dst, shift_amount, 0x5); 1060 } 1061 1062 void shr_cl(Register dst) { 1063 shift(dst, 0x5); 1064 } 1065 1066 void shrl_cl(Register dst) { 1067 shift_32(dst, 0x5); 1068 } 1069 1070 void shrl(Register dst, Immediate shift_amount) { 1071 shift_32(dst, shift_amount, 0x5); 1072 } 1073 1074 void store_rax(void* dst, RelocInfo::Mode mode); 1075 void store_rax(ExternalReference ref); 1076 1077 void subq(Register dst, Register src) { 1078 arithmetic_op(0x2B, dst, src); 1079 } 1080 1081 void subq(Register dst, const Operand& src) { 1082 arithmetic_op(0x2B, dst, src); 1083 } 1084 1085 void subq(const Operand& dst, Register src) { 1086 arithmetic_op(0x29, src, dst); 1087 } 1088 1089 void subq(Register dst, Immediate src) { 1090 immediate_arithmetic_op(0x5, dst, src); 1091 } 1092 1093 void subq(const Operand& dst, Immediate src) { 1094 immediate_arithmetic_op(0x5, dst, src); 1095 } 1096 1097 void subl(Register dst, Register src) { 1098 arithmetic_op_32(0x2B, dst, src); 1099 } 1100 1101 void subl(Register dst, const Operand& src) { 1102 arithmetic_op_32(0x2B, dst, src); 1103 } 1104 1105 void subl(const Operand& dst, Immediate src) { 1106 immediate_arithmetic_op_32(0x5, dst, src); 1107 } 1108 1109 void subl(Register dst, Immediate src) { 1110 immediate_arithmetic_op_32(0x5, dst, src); 1111 } 1112 1113 void subb(Register dst, Immediate src) { 1114 immediate_arithmetic_op_8(0x5, dst, src); 1115 } 1116 1117 void testb(Register dst, Register src); 1118 void testb(Register reg, Immediate mask); 1119 void testb(const Operand& op, Immediate mask); 1120 void testb(const Operand& op, Register reg); 1121 void testl(Register dst, Register src); 1122 void testl(Register reg, Immediate mask); 1123 void testl(const Operand& op, Immediate mask); 1124 void testq(const Operand& op, Register reg); 1125 void testq(Register dst, Register src); 1126 void testq(Register dst, Immediate mask); 1127 1128 void xor_(Register dst, Register src) { 1129 if (dst.code() == src.code()) { 1130 arithmetic_op_32(0x33, dst, src); 1131 } else { 1132 arithmetic_op(0x33, dst, src); 1133 } 1134 } 1135 1136 void xorl(Register dst, Register src) { 1137 arithmetic_op_32(0x33, dst, src); 1138 } 1139 1140 void xorl(Register dst, const Operand& src) { 1141 arithmetic_op_32(0x33, dst, src); 1142 } 1143 1144 void xorl(Register dst, Immediate src) { 1145 immediate_arithmetic_op_32(0x6, dst, src); 1146 } 1147 1148 void xorl(const Operand& dst, Immediate src) { 1149 immediate_arithmetic_op_32(0x6, dst, src); 1150 } 1151 1152 void xor_(Register dst, const Operand& src) { 1153 arithmetic_op(0x33, dst, src); 1154 } 1155 1156 void xor_(const Operand& dst, Register src) { 1157 arithmetic_op(0x31, src, dst); 1158 } 1159 1160 void xor_(Register dst, Immediate src) { 1161 immediate_arithmetic_op(0x6, dst, src); 1162 } 1163 1164 void xor_(const Operand& dst, Immediate src) { 1165 immediate_arithmetic_op(0x6, dst, src); 1166 } 1167 1168 // Bit operations. 1169 void bt(const Operand& dst, Register src); 1170 void bts(const Operand& dst, Register src); 1171 1172 // Miscellaneous 1173 void clc(); 1174 void cld(); 1175 void cpuid(); 1176 void hlt(); 1177 void int3(); 1178 void nop(); 1179 void rdtsc(); 1180 void ret(int imm16); 1181 void setcc(Condition cc, Register reg); 1182 1183 // Label operations & relative jumps (PPUM Appendix D) 1184 // 1185 // Takes a branch opcode (cc) and a label (L) and generates 1186 // either a backward branch or a forward branch and links it 1187 // to the label fixup chain. Usage: 1188 // 1189 // Label L; // unbound label 1190 // j(cc, &L); // forward branch to unbound label 1191 // bind(&L); // bind label to the current pc 1192 // j(cc, &L); // backward branch to bound label 1193 // bind(&L); // illegal: a label may be bound only once 1194 // 1195 // Note: The same Label can be used for forward and backward branches 1196 // but it may be bound only once. 1197 1198 void bind(Label* L); // binds an unbound label L to the current code position 1199 1200 // Calls 1201 // Call near relative 32-bit displacement, relative to next instruction. 1202 void call(Label* L); 1203 void call(Address entry, RelocInfo::Mode rmode); 1204 void call(Handle<Code> target, 1205 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET, 1206 TypeFeedbackId ast_id = TypeFeedbackId::None()); 1207 1208 // Calls directly to the given address using a relative offset. 1209 // Should only ever be used in Code objects for calls within the 1210 // same Code object. Should not be used when generating new code (use labels), 1211 // but only when patching existing code. 1212 void call(Address target); 1213 1214 // Call near absolute indirect, address in register 1215 void call(Register adr); 1216 1217 // Call near indirect 1218 void call(const Operand& operand); 1219 1220 // Jumps 1221 // Jump short or near relative. 1222 // Use a 32-bit signed displacement. 1223 // Unconditional jump to L 1224 void jmp(Label* L, Label::Distance distance = Label::kFar); 1225 void jmp(Address entry, RelocInfo::Mode rmode); 1226 void jmp(Handle<Code> target, RelocInfo::Mode rmode); 1227 1228 // Jump near absolute indirect (r64) 1229 void jmp(Register adr); 1230 1231 // Jump near absolute indirect (m64) 1232 void jmp(const Operand& src); 1233 1234 // Conditional jumps 1235 void j(Condition cc, 1236 Label* L, 1237 Label::Distance distance = Label::kFar); 1238 void j(Condition cc, Address entry, RelocInfo::Mode rmode); 1239 void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode); 1240 1241 // Floating-point operations 1242 void fld(int i); 1243 1244 void fld1(); 1245 void fldz(); 1246 void fldpi(); 1247 void fldln2(); 1248 1249 void fld_s(const Operand& adr); 1250 void fld_d(const Operand& adr); 1251 1252 void fstp_s(const Operand& adr); 1253 void fstp_d(const Operand& adr); 1254 void fstp(int index); 1255 1256 void fild_s(const Operand& adr); 1257 void fild_d(const Operand& adr); 1258 1259 void fist_s(const Operand& adr); 1260 1261 void fistp_s(const Operand& adr); 1262 void fistp_d(const Operand& adr); 1263 1264 void fisttp_s(const Operand& adr); 1265 void fisttp_d(const Operand& adr); 1266 1267 void fabs(); 1268 void fchs(); 1269 1270 void fadd(int i); 1271 void fsub(int i); 1272 void fmul(int i); 1273 void fdiv(int i); 1274 1275 void fisub_s(const Operand& adr); 1276 1277 void faddp(int i = 1); 1278 void fsubp(int i = 1); 1279 void fsubrp(int i = 1); 1280 void fmulp(int i = 1); 1281 void fdivp(int i = 1); 1282 void fprem(); 1283 void fprem1(); 1284 1285 void fxch(int i = 1); 1286 void fincstp(); 1287 void ffree(int i = 0); 1288 1289 void ftst(); 1290 void fucomp(int i); 1291 void fucompp(); 1292 void fucomi(int i); 1293 void fucomip(); 1294 1295 void fcompp(); 1296 void fnstsw_ax(); 1297 void fwait(); 1298 void fnclex(); 1299 1300 void fsin(); 1301 void fcos(); 1302 void fptan(); 1303 void fyl2x(); 1304 void f2xm1(); 1305 void fscale(); 1306 void fninit(); 1307 1308 void frndint(); 1309 1310 void sahf(); 1311 1312 // SSE2 instructions 1313 void movd(XMMRegister dst, Register src); 1314 void movd(Register dst, XMMRegister src); 1315 void movq(XMMRegister dst, Register src); 1316 void movq(Register dst, XMMRegister src); 1317 void movq(XMMRegister dst, XMMRegister src); 1318 void extractps(Register dst, XMMRegister src, byte imm8); 1319 1320 // Don't use this unless it's important to keep the 1321 // top half of the destination register unchanged. 1322 // Used movaps when moving double values and movq for integer 1323 // values in xmm registers. 1324 void movsd(XMMRegister dst, XMMRegister src); 1325 1326 void movsd(const Operand& dst, XMMRegister src); 1327 void movsd(XMMRegister dst, const Operand& src); 1328 1329 void movdqa(const Operand& dst, XMMRegister src); 1330 void movdqa(XMMRegister dst, const Operand& src); 1331 1332 void movdqu(const Operand& dst, XMMRegister src); 1333 void movdqu(XMMRegister dst, const Operand& src); 1334 1335 void movapd(XMMRegister dst, XMMRegister src); 1336 void movaps(XMMRegister dst, XMMRegister src); 1337 1338 void movss(XMMRegister dst, const Operand& src); 1339 void movss(const Operand& dst, XMMRegister src); 1340 1341 void cvttss2si(Register dst, const Operand& src); 1342 void cvttss2si(Register dst, XMMRegister src); 1343 void cvttsd2si(Register dst, const Operand& src); 1344 void cvttsd2si(Register dst, XMMRegister src); 1345 void cvttsd2siq(Register dst, XMMRegister src); 1346 1347 void cvtlsi2sd(XMMRegister dst, const Operand& src); 1348 void cvtlsi2sd(XMMRegister dst, Register src); 1349 void cvtqsi2sd(XMMRegister dst, const Operand& src); 1350 void cvtqsi2sd(XMMRegister dst, Register src); 1351 1352 void cvtlsi2ss(XMMRegister dst, Register src); 1353 1354 void cvtss2sd(XMMRegister dst, XMMRegister src); 1355 void cvtss2sd(XMMRegister dst, const Operand& src); 1356 void cvtsd2ss(XMMRegister dst, XMMRegister src); 1357 1358 void cvtsd2si(Register dst, XMMRegister src); 1359 void cvtsd2siq(Register dst, XMMRegister src); 1360 1361 void addsd(XMMRegister dst, XMMRegister src); 1362 void addsd(XMMRegister dst, const Operand& src); 1363 void subsd(XMMRegister dst, XMMRegister src); 1364 void mulsd(XMMRegister dst, XMMRegister src); 1365 void mulsd(XMMRegister dst, const Operand& src); 1366 void divsd(XMMRegister dst, XMMRegister src); 1367 1368 void andpd(XMMRegister dst, XMMRegister src); 1369 void orpd(XMMRegister dst, XMMRegister src); 1370 void xorpd(XMMRegister dst, XMMRegister src); 1371 void xorps(XMMRegister dst, XMMRegister src); 1372 void sqrtsd(XMMRegister dst, XMMRegister src); 1373 1374 void ucomisd(XMMRegister dst, XMMRegister src); 1375 void ucomisd(XMMRegister dst, const Operand& src); 1376 1377 enum RoundingMode { 1378 kRoundToNearest = 0x0, 1379 kRoundDown = 0x1, 1380 kRoundUp = 0x2, 1381 kRoundToZero = 0x3 1382 }; 1383 1384 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode); 1385 1386 void movmskpd(Register dst, XMMRegister src); 1387 void movmskps(Register dst, XMMRegister src); 1388 1389 // The first argument is the reg field, the second argument is the r/m field. 1390 void emit_sse_operand(XMMRegister dst, XMMRegister src); 1391 void emit_sse_operand(XMMRegister reg, const Operand& adr); 1392 void emit_sse_operand(XMMRegister dst, Register src); 1393 void emit_sse_operand(Register dst, XMMRegister src); 1394 1395 // Debugging 1396 void Print(); 1397 1398 // Check the code size generated from label to here. 1399 int SizeOfCodeGeneratedSince(Label* label) { 1400 return pc_offset() - label->pos(); 1401 } 1402 1403 // Mark address of the ExitJSFrame code. 1404 void RecordJSReturn(); 1405 1406 // Mark address of a debug break slot. 1407 void RecordDebugBreakSlot(); 1408 1409 // Record a comment relocation entry that can be used by a disassembler. 1410 // Use --code-comments to enable. 1411 void RecordComment(const char* msg, bool force = false); 1412 1413 // Writes a single word of data in the code stream. 1414 // Used for inline tables, e.g., jump-tables. 1415 void db(uint8_t data); 1416 void dd(uint32_t data); 1417 1418 PositionsRecorder* positions_recorder() { return &positions_recorder_; } 1419 1420 // Check if there is less than kGap bytes available in the buffer. 1421 // If this is the case, we need to grow the buffer before emitting 1422 // an instruction or relocation information. 1423 inline bool buffer_overflow() const { 1424 return pc_ >= reloc_info_writer.pos() - kGap; 1425 } 1426 1427 // Get the number of bytes available in the buffer. 1428 inline int available_space() const { 1429 return static_cast<int>(reloc_info_writer.pos() - pc_); 1430 } 1431 1432 static bool IsNop(Address addr); 1433 1434 // Avoid overflows for displacements etc. 1435 static const int kMaximalBufferSize = 512*MB; 1436 1437 byte byte_at(int pos) { return buffer_[pos]; } 1438 void set_byte_at(int pos, byte value) { buffer_[pos] = value; } 1439 1440 private: 1441 byte* addr_at(int pos) { return buffer_ + pos; } 1442 uint32_t long_at(int pos) { 1443 return *reinterpret_cast<uint32_t*>(addr_at(pos)); 1444 } 1445 void long_at_put(int pos, uint32_t x) { 1446 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x; 1447 } 1448 1449 // code emission 1450 void GrowBuffer(); 1451 1452 void emit(byte x) { *pc_++ = x; } 1453 inline void emitl(uint32_t x); 1454 inline void emitp(void* x, RelocInfo::Mode rmode); 1455 inline void emitq(uint64_t x, RelocInfo::Mode rmode); 1456 inline void emitw(uint16_t x); 1457 inline void emit_code_target(Handle<Code> target, 1458 RelocInfo::Mode rmode, 1459 TypeFeedbackId ast_id = TypeFeedbackId::None()); 1460 inline void emit_runtime_entry(Address entry, RelocInfo::Mode rmode); 1461 void emit(Immediate x) { emitl(x.value_); } 1462 1463 // Emits a REX prefix that encodes a 64-bit operand size and 1464 // the top bit of both register codes. 1465 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1466 // REX.W is set. 1467 inline void emit_rex_64(XMMRegister reg, Register rm_reg); 1468 inline void emit_rex_64(Register reg, XMMRegister rm_reg); 1469 inline void emit_rex_64(Register reg, Register rm_reg); 1470 1471 // Emits a REX prefix that encodes a 64-bit operand size and 1472 // the top bit of the destination, index, and base register codes. 1473 // The high bit of reg is used for REX.R, the high bit of op's base 1474 // register is used for REX.B, and the high bit of op's index register 1475 // is used for REX.X. REX.W is set. 1476 inline void emit_rex_64(Register reg, const Operand& op); 1477 inline void emit_rex_64(XMMRegister reg, const Operand& op); 1478 1479 // Emits a REX prefix that encodes a 64-bit operand size and 1480 // the top bit of the register code. 1481 // The high bit of register is used for REX.B. 1482 // REX.W is set and REX.R and REX.X are clear. 1483 inline void emit_rex_64(Register rm_reg); 1484 1485 // Emits a REX prefix that encodes a 64-bit operand size and 1486 // the top bit of the index and base register codes. 1487 // The high bit of op's base register is used for REX.B, and the high 1488 // bit of op's index register is used for REX.X. 1489 // REX.W is set and REX.R clear. 1490 inline void emit_rex_64(const Operand& op); 1491 1492 // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size. 1493 void emit_rex_64() { emit(0x48); } 1494 1495 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1496 // REX.W is clear. 1497 inline void emit_rex_32(Register reg, Register rm_reg); 1498 1499 // The high bit of reg is used for REX.R, the high bit of op's base 1500 // register is used for REX.B, and the high bit of op's index register 1501 // is used for REX.X. REX.W is cleared. 1502 inline void emit_rex_32(Register reg, const Operand& op); 1503 1504 // High bit of rm_reg goes to REX.B. 1505 // REX.W, REX.R and REX.X are clear. 1506 inline void emit_rex_32(Register rm_reg); 1507 1508 // High bit of base goes to REX.B and high bit of index to REX.X. 1509 // REX.W and REX.R are clear. 1510 inline void emit_rex_32(const Operand& op); 1511 1512 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1513 // REX.W is cleared. If no REX bits are set, no byte is emitted. 1514 inline void emit_optional_rex_32(Register reg, Register rm_reg); 1515 1516 // The high bit of reg is used for REX.R, the high bit of op's base 1517 // register is used for REX.B, and the high bit of op's index register 1518 // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing 1519 // is emitted. 1520 inline void emit_optional_rex_32(Register reg, const Operand& op); 1521 1522 // As for emit_optional_rex_32(Register, Register), except that 1523 // the registers are XMM registers. 1524 inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base); 1525 1526 // As for emit_optional_rex_32(Register, Register), except that 1527 // one of the registers is an XMM registers. 1528 inline void emit_optional_rex_32(XMMRegister reg, Register base); 1529 1530 // As for emit_optional_rex_32(Register, Register), except that 1531 // one of the registers is an XMM registers. 1532 inline void emit_optional_rex_32(Register reg, XMMRegister base); 1533 1534 // As for emit_optional_rex_32(Register, const Operand&), except that 1535 // the register is an XMM register. 1536 inline void emit_optional_rex_32(XMMRegister reg, const Operand& op); 1537 1538 // Optionally do as emit_rex_32(Register) if the register number has 1539 // the high bit set. 1540 inline void emit_optional_rex_32(Register rm_reg); 1541 1542 // Optionally do as emit_rex_32(const Operand&) if the operand register 1543 // numbers have a high bit set. 1544 inline void emit_optional_rex_32(const Operand& op); 1545 1546 1547 // Emit the ModR/M byte, and optionally the SIB byte and 1548 // 1- or 4-byte offset for a memory operand. Also encodes 1549 // the second operand of the operation, a register or operation 1550 // subcode, into the reg field of the ModR/M byte. 1551 void emit_operand(Register reg, const Operand& adr) { 1552 emit_operand(reg.low_bits(), adr); 1553 } 1554 1555 // Emit the ModR/M byte, and optionally the SIB byte and 1556 // 1- or 4-byte offset for a memory operand. Also used to encode 1557 // a three-bit opcode extension into the ModR/M byte. 1558 void emit_operand(int rm, const Operand& adr); 1559 1560 // Emit a ModR/M byte with registers coded in the reg and rm_reg fields. 1561 void emit_modrm(Register reg, Register rm_reg) { 1562 emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits()); 1563 } 1564 1565 // Emit a ModR/M byte with an operation subcode in the reg field and 1566 // a register in the rm_reg field. 1567 void emit_modrm(int code, Register rm_reg) { 1568 ASSERT(is_uint3(code)); 1569 emit(0xC0 | code << 3 | rm_reg.low_bits()); 1570 } 1571 1572 // Emit the code-object-relative offset of the label's position 1573 inline void emit_code_relative_offset(Label* label); 1574 1575 // Emit machine code for one of the operations ADD, ADC, SUB, SBC, 1576 // AND, OR, XOR, or CMP. The encodings of these operations are all 1577 // similar, differing just in the opcode or in the reg field of the 1578 // ModR/M byte. 1579 void arithmetic_op_16(byte opcode, Register reg, Register rm_reg); 1580 void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg); 1581 void arithmetic_op_32(byte opcode, Register reg, Register rm_reg); 1582 void arithmetic_op_32(byte opcode, Register reg, const Operand& rm_reg); 1583 void arithmetic_op(byte opcode, Register reg, Register rm_reg); 1584 void arithmetic_op(byte opcode, Register reg, const Operand& rm_reg); 1585 void immediate_arithmetic_op(byte subcode, Register dst, Immediate src); 1586 void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src); 1587 // Operate on a byte in memory or register. 1588 void immediate_arithmetic_op_8(byte subcode, 1589 Register dst, 1590 Immediate src); 1591 void immediate_arithmetic_op_8(byte subcode, 1592 const Operand& dst, 1593 Immediate src); 1594 // Operate on a word in memory or register. 1595 void immediate_arithmetic_op_16(byte subcode, 1596 Register dst, 1597 Immediate src); 1598 void immediate_arithmetic_op_16(byte subcode, 1599 const Operand& dst, 1600 Immediate src); 1601 // Operate on a 32-bit word in memory or register. 1602 void immediate_arithmetic_op_32(byte subcode, 1603 Register dst, 1604 Immediate src); 1605 void immediate_arithmetic_op_32(byte subcode, 1606 const Operand& dst, 1607 Immediate src); 1608 1609 // Emit machine code for a shift operation. 1610 void shift(Register dst, Immediate shift_amount, int subcode); 1611 void shift_32(Register dst, Immediate shift_amount, int subcode); 1612 // Shift dst by cl % 64 bits. 1613 void shift(Register dst, int subcode); 1614 void shift_32(Register dst, int subcode); 1615 1616 void emit_farith(int b1, int b2, int i); 1617 1618 // labels 1619 // void print(Label* L); 1620 void bind_to(Label* L, int pos); 1621 1622 // record reloc info for current pc_ 1623 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1624 1625 friend class CodePatcher; 1626 friend class EnsureSpace; 1627 friend class RegExpMacroAssemblerX64; 1628 1629 // code generation 1630 RelocInfoWriter reloc_info_writer; 1631 1632 List< Handle<Code> > code_targets_; 1633 1634 PositionsRecorder positions_recorder_; 1635 friend class PositionsRecorder; 1636 }; 1637 1638 1639 // Helper class that ensures that there is enough space for generating 1640 // instructions and relocation information. The constructor makes 1641 // sure that there is enough space and (in debug mode) the destructor 1642 // checks that we did not generate too much. 1643 class EnsureSpace BASE_EMBEDDED { 1644 public: 1645 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) { 1646 if (assembler_->buffer_overflow()) assembler_->GrowBuffer(); 1647 #ifdef DEBUG 1648 space_before_ = assembler_->available_space(); 1649 #endif 1650 } 1651 1652 #ifdef DEBUG 1653 ~EnsureSpace() { 1654 int bytes_generated = space_before_ - assembler_->available_space(); 1655 ASSERT(bytes_generated < assembler_->kGap); 1656 } 1657 #endif 1658 1659 private: 1660 Assembler* assembler_; 1661 #ifdef DEBUG 1662 int space_before_; 1663 #endif 1664 }; 1665 1666 } } // namespace v8::internal 1667 1668 #endif // V8_X64_ASSEMBLER_X64_H_ 1669