1 /* ********************************************************************* 2 * BCM1280/BCM1400 Board Support Package 3 * 4 * SCD Constants and Macros File: bcm1480_scd.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the System Control and Debug module. 8 * 9 * BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004,2005 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 ********************************************************************* */ 31 32 #ifndef _BCM1480_SCD_H 33 #define _BCM1480_SCD_H 34 35 #include "sb1250_defs.h" 36 37 /* ********************************************************************* 38 * Pull in the BCM1250's SCD since lots of stuff is the same. 39 ********************************************************************* */ 40 41 #include "sb1250_scd.h" 42 43 /* ********************************************************************* 44 * Some general notes: 45 * 46 * This file is basically a "what's new" header file. Since the 47 * BCM1250 and the new BCM1480 (and derivatives) share many common 48 * features, this file contains only what's new or changed from 49 * the 1250. (above, you can see that we include the 1250 symbols 50 * to get the base functionality). 51 * 52 * In software, be sure to use the correct symbols, particularly 53 * for blocks that are different between the two chip families. 54 * All BCM1480-specific symbols have _BCM1480_ in their names, 55 * and all BCM1250-specific and "base" functions that are common in 56 * both chips have no special names (this is for compatibility with 57 * older include files). Therefore, if you're working with the 58 * SCD, which is very different on each chip, A_SCD_xxx implies 59 * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 60 * version. 61 ********************************************************************* */ 62 63 /* ********************************************************************* 64 * System control/debug registers 65 ********************************************************************* */ 66 67 /* 68 * System Identification and Revision Register (Table 12) 69 * Register: SCD_SYSTEM_REVISION 70 * This register is field compatible with the 1250. 71 */ 72 73 /* 74 * New part definitions 75 */ 76 77 #define K_SYS_PART_BCM1480 0x1406 78 #define K_SYS_PART_BCM1280 0x1206 79 #define K_SYS_PART_BCM1455 0x1407 80 #define K_SYS_PART_BCM1255 0x1257 81 #define K_SYS_PART_BCM1158 0x1156 82 83 /* 84 * Manufacturing Information Register (Table 14) 85 * Register: SCD_SYSTEM_MANUF 86 */ 87 88 /* 89 * System Configuration Register (Table 15) 90 * Register: SCD_SYSTEM_CFG 91 * Entire register is different from 1250, all new constants below 92 */ 93 94 #define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) 95 #define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) 96 #define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) 97 #define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) 98 #define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) 99 #define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) 100 101 #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) 102 #define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) 103 #define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) 104 #define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) 105 106 #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) 107 #define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) 108 #define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) 109 #define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) 110 111 #define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 112 #define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) 113 114 #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) 115 #define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) 116 #define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) 117 #define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) 118 #define K_BCM1480_SYS_BOOT_MODE_ROM32 0 119 #define K_BCM1480_SYS_BOOT_MODE_ROM8 1 120 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 121 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 122 #define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) 123 124 #define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) 125 #define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) 126 #define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 127 #define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) 128 #define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) 129 #define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) 130 131 #define S_BCM1480_SYS_CONFIG 26 132 #define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) 133 #define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) 134 #define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) 135 136 #define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) 137 138 #define S_BCM1480_SYS_NODEID 47 139 #define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) 140 #define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) 141 #define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) 142 143 #define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) 144 #define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) 145 #define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) 146 #define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) 147 #define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) 148 #define S_BCM1480_SYS_DISABLECPU0 56 149 #define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) 150 #define S_BCM1480_SYS_DISABLECPU1 57 151 #define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) 152 #define S_BCM1480_SYS_DISABLECPU2 58 153 #define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) 154 #define S_BCM1480_SYS_DISABLECPU3 59 155 #define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) 156 157 #define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) 158 #define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) 159 #define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) 160 #define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) 161 162 /* 163 * Scratch Register (Table 16) 164 * Register: SCD_SYSTEM_SCRATCH 165 * Same as BCM1250 166 */ 167 168 169 /* 170 * Mailbox Registers (Table 17) 171 * Registers: SCD_MBOX_{0,1}_CPU_x 172 * Same as BCM1250 173 */ 174 175 176 /* 177 * See bcm1480_int.h for interrupt mapper registers. 178 */ 179 180 181 /* 182 * Watchdog Timer Initial Count Registers (Table 23) 183 * Registers: SCD_WDOG_INIT_CNT_x 184 * 185 * The watchdogs are almost the same as the 1250, except 186 * the configuration register has more bits to control the 187 * other CPUs. 188 */ 189 190 191 /* 192 * Watchdog Timer Configuration Registers (Table 25) 193 * Registers: SCD_WDOG_CFG_x 194 */ 195 196 #define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) 197 198 #define S_BCM1480_SCD_WDOG_RESET_TYPE 2 199 #define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) 200 #define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) 201 #define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) 202 203 #define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 204 #define K_BCM1480_SCD_WDOG_RESET_SOFT 1 205 #define K_BCM1480_SCD_WDOG_RESET_CPU0 3 206 #define K_BCM1480_SCD_WDOG_RESET_CPU1 5 207 #define K_BCM1480_SCD_WDOG_RESET_CPU2 9 208 #define K_BCM1480_SCD_WDOG_RESET_CPU3 17 209 #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 210 211 212 #define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) 213 214 /* 215 * General Timer Initial Count Registers (Table 26) 216 * Registers: SCD_TIMER_INIT_x 217 * 218 * The timer registers are the same as the BCM1250 219 */ 220 221 222 /* 223 * ZBbus Count Register (Table 29) 224 * Register: ZBBUS_CYCLE_COUNT 225 * 226 * Same as BCM1250 227 */ 228 229 /* 230 * ZBbus Compare Registers (Table 30) 231 * Registers: ZBBUS_CYCLE_CPx 232 * 233 * Same as BCM1250 234 */ 235 236 237 /* 238 * System Performance Counter Configuration Register (Table 31) 239 * Register: PERF_CNT_CFG_0 240 * 241 * SPC_CFG_SRC[0-3] is the same as the 1250. 242 * SPC_CFG_SRC[4-7] only exist on the 1480 243 * The clear/enable bits are in different locations on the 1250 and 1480. 244 */ 245 246 #define S_SPC_CFG_SRC4 32 247 #define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) 248 #define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) 249 #define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) 250 251 #define S_SPC_CFG_SRC5 40 252 #define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) 253 #define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) 254 #define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) 255 256 #define S_SPC_CFG_SRC6 48 257 #define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) 258 #define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) 259 #define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) 260 261 #define S_SPC_CFG_SRC7 56 262 #define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) 263 #define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) 264 #define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) 265 266 /* 267 * System Performance Counter Control Register (Table 32) 268 * Register: PERF_CNT_CFG_1 269 * BCM1480 specific 270 */ 271 #define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) 272 #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) 273 #if SIBYTE_HDR_FEATURE_CHIP(1480) 274 #define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR 275 #define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE 276 #endif 277 278 /* 279 * System Performance Counters (Table 33) 280 * Registers: PERF_CNT_x 281 */ 282 283 #define S_BCM1480_SPC_CNT_COUNT 0 284 #define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) 285 #define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) 286 #define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) 287 288 #define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) 289 290 291 /* 292 * Bus Watcher Error Status Register (Tables 36, 37) 293 * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG 294 * Same as BCM1250. 295 */ 296 297 /* 298 * Bus Watcher Error Data Registers (Table 38) 299 * Registers: BUS_ERR_DATA_x 300 * Same as BCM1250. 301 */ 302 303 /* 304 * Bus Watcher L2 ECC Counter Register (Table 39) 305 * Register: BUS_L2_ERRORS 306 * Same as BCM1250. 307 */ 308 309 310 /* 311 * Bus Watcher Memory and I/O Error Counter Register (Table 40) 312 * Register: BUS_MEM_IO_ERRORS 313 * Same as BCM1250. 314 */ 315 316 317 /* 318 * Address Trap Registers 319 * 320 * Register layout same as BCM1250, almost. The bus agents 321 * are different, and the address trap configuration bits are 322 * slightly different. 323 */ 324 325 #define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) 326 #define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) 327 328 #define S_BCM1480_ATRAP_CFG_CNT 0 329 #define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) 330 #define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) 331 #define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) 332 333 #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 334 #define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 335 #define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) 336 #define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 337 #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 338 339 #define S_BCM1480_ATRAP_CFG_AGENTID 8 340 #define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) 341 #define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) 342 #define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) 343 344 345 #define K_BCM1480_BUS_AGENT_CPU0 0 346 #define K_BCM1480_BUS_AGENT_CPU1 1 347 #define K_BCM1480_BUS_AGENT_NC 2 348 #define K_BCM1480_BUS_AGENT_IOB 3 349 #define K_BCM1480_BUS_AGENT_SCD 4 350 #define K_BCM1480_BUS_AGENT_L2C 6 351 #define K_BCM1480_BUS_AGENT_MC 7 352 #define K_BCM1480_BUS_AGENT_CPU2 8 353 #define K_BCM1480_BUS_AGENT_CPU3 9 354 #define K_BCM1480_BUS_AGENT_PM 10 355 356 #define S_BCM1480_ATRAP_CFG_CATTR 12 357 #define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) 358 #define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) 359 #define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) 360 361 #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 362 #define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 363 #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 364 #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 365 366 #define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) 367 368 369 /* 370 * Trace Event Registers (Table 47) 371 * Same as BCM1250. 372 */ 373 374 /* 375 * Trace Sequence Control Registers (Table 48) 376 * Registers: TRACE_SEQUENCE_x 377 * 378 * Same as BCM1250 except for two new fields. 379 */ 380 381 382 #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) 383 384 #define S_BCM1480_SCD_TRSEQ_SWFUNC 26 385 #define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) 386 #define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) 387 #define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) 388 389 /* 390 * Trace Control Register (Table 49) 391 * Register: TRACE_CFG 392 * 393 * BCM1480 changes to this register (other than location of the CUR_ADDR field) 394 * are defined below. 395 */ 396 397 #define S_BCM1480_SCD_TRACE_CFG_MODE 16 398 #define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) 399 #define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) 400 #define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) 401 402 #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 403 #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 404 #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 405 406 #endif /* _BCM1480_SCD_H */ 407
