1 ; RUN: llc < %s -march=arm -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp | FileCheck %s 2 3 ; This test checks that the VMLxForwarting feature is disabled for A15. 4 ; CHECK: fun_a: 5 define <4 x i32> @fun_a(<4 x i32> %x, <4 x i32> %y) nounwind{ 6 %1 = add <4 x i32> %x, %y 7 ; CHECK-NOT: vmul 8 ; CHECK: vmla 9 %2 = mul <4 x i32> %1, %1 10 %3 = add <4 x i32> %y, %2 11 ret <4 x i32> %3 12 } 13 14 ; This tests checks that VMLA FP patterns can be matched in instruction selection when targeting 15 ; Cortex-A15. 16 ; CHECK: fun_b: 17 define <4 x float> @fun_b(<4 x float> %x, <4 x float> %y, <4 x float> %z) nounwind{ 18 ; CHECK: vmla.f32 19 %t = fmul <4 x float> %x, %y 20 %r = fadd <4 x float> %t, %z 21 ret <4 x float> %r 22 } 23 24 ; This tests checks that FP VMLA instructions are not expanded into separate multiply/addition 25 ; operations when targeting Cortex-A15. 26 ; CHECK: fun_c: 27 define <4 x float> @fun_c(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %u, <4 x float> %v) nounwind{ 28 ; CHECK: vmla.f32 29 %t1 = fmul <4 x float> %x, %y 30 %r1 = fadd <4 x float> %t1, %z 31 ; CHECK: vmla.f32 32 %t2 = fmul <4 x float> %u, %v 33 %r2 = fadd <4 x float> %t2, %r1 34 ret <4 x float> %r2 35 } 36 37
