1 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM 2 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM 3 ; rdar://10418009 4 5 define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp { 6 entry: 7 ; ARM: t1 8 %add.ptr = getelementptr inbounds i16* %a, i64 -8 9 %0 = load i16* %add.ptr, align 2 10 ; ARM: ldrh r0, [r0, #-16] 11 ret i16 %0 12 } 13 14 define zeroext i16 @t2(i16* nocapture %a) nounwind uwtable readonly ssp { 15 entry: 16 ; ARM: t2 17 %add.ptr = getelementptr inbounds i16* %a, i64 -16 18 %0 = load i16* %add.ptr, align 2 19 ; ARM: ldrh r0, [r0, #-32] 20 ret i16 %0 21 } 22 23 define zeroext i16 @t3(i16* nocapture %a) nounwind uwtable readonly ssp { 24 entry: 25 ; ARM: t3 26 %add.ptr = getelementptr inbounds i16* %a, i64 -127 27 %0 = load i16* %add.ptr, align 2 28 ; ARM: ldrh r0, [r0, #-254] 29 ret i16 %0 30 } 31 32 define zeroext i16 @t4(i16* nocapture %a) nounwind uwtable readonly ssp { 33 entry: 34 ; ARM: t4 35 %add.ptr = getelementptr inbounds i16* %a, i64 -128 36 %0 = load i16* %add.ptr, align 2 37 ; ARM: mvn r{{[1-9]}}, #255 38 ; ARM: add r0, r0, r{{[1-9]}} 39 ; ARM: ldrh r0, [r0] 40 ret i16 %0 41 } 42 43 define zeroext i16 @t5(i16* nocapture %a) nounwind uwtable readonly ssp { 44 entry: 45 ; ARM: t5 46 %add.ptr = getelementptr inbounds i16* %a, i64 8 47 %0 = load i16* %add.ptr, align 2 48 ; ARM: ldrh r0, [r0, #16] 49 ret i16 %0 50 } 51 52 define zeroext i16 @t6(i16* nocapture %a) nounwind uwtable readonly ssp { 53 entry: 54 ; ARM: t6 55 %add.ptr = getelementptr inbounds i16* %a, i64 16 56 %0 = load i16* %add.ptr, align 2 57 ; ARM: ldrh r0, [r0, #32] 58 ret i16 %0 59 } 60 61 define zeroext i16 @t7(i16* nocapture %a) nounwind uwtable readonly ssp { 62 entry: 63 ; ARM: t7 64 %add.ptr = getelementptr inbounds i16* %a, i64 127 65 %0 = load i16* %add.ptr, align 2 66 ; ARM: ldrh r0, [r0, #254] 67 ret i16 %0 68 } 69 70 define zeroext i16 @t8(i16* nocapture %a) nounwind uwtable readonly ssp { 71 entry: 72 ; ARM: t8 73 %add.ptr = getelementptr inbounds i16* %a, i64 128 74 %0 = load i16* %add.ptr, align 2 75 ; ARM: add r0, r0, #256 76 ; ARM: ldrh r0, [r0] 77 ret i16 %0 78 } 79 80 define void @t9(i16* nocapture %a) nounwind uwtable ssp { 81 entry: 82 ; ARM: t9 83 %add.ptr = getelementptr inbounds i16* %a, i64 -8 84 store i16 0, i16* %add.ptr, align 2 85 ; ARM: strh r1, [r0, #-16] 86 ret void 87 } 88 89 ; mvn r1, #255 90 ; strh r2, [r0, r1] 91 define void @t10(i16* nocapture %a) nounwind uwtable ssp { 92 entry: 93 ; ARM: t10 94 %add.ptr = getelementptr inbounds i16* %a, i64 -128 95 store i16 0, i16* %add.ptr, align 2 96 ; ARM: mvn r{{[1-9]}}, #255 97 ; ARM: add r0, r0, r{{[1-9]}} 98 ; ARM: strh r{{[1-9]}}, [r0] 99 ret void 100 } 101 102 define void @t11(i16* nocapture %a) nounwind uwtable ssp { 103 entry: 104 ; ARM: t11 105 %add.ptr = getelementptr inbounds i16* %a, i64 8 106 store i16 0, i16* %add.ptr, align 2 107 ; ARM: strh r{{[1-9]}}, [r0, #16] 108 ret void 109 } 110 111 ; mov r1, #256 112 ; strh r2, [r0, r1] 113 define void @t12(i16* nocapture %a) nounwind uwtable ssp { 114 entry: 115 ; ARM: t12 116 %add.ptr = getelementptr inbounds i16* %a, i64 128 117 store i16 0, i16* %add.ptr, align 2 118 ; ARM: add r0, r0, #256 119 ; ARM: strh r{{[1-9]}}, [r0] 120 ret void 121 } 122 123 define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp { 124 entry: 125 ; ARM: t13 126 %add.ptr = getelementptr inbounds i8* %a, i64 -8 127 %0 = load i8* %add.ptr, align 2 128 ; ARM: ldrsb r0, [r0, #-8] 129 ret i8 %0 130 } 131 132 define signext i8 @t14(i8* nocapture %a) nounwind uwtable readonly ssp { 133 entry: 134 ; ARM: t14 135 %add.ptr = getelementptr inbounds i8* %a, i64 -255 136 %0 = load i8* %add.ptr, align 2 137 ; ARM: ldrsb r0, [r0, #-255] 138 ret i8 %0 139 } 140 141 define signext i8 @t15(i8* nocapture %a) nounwind uwtable readonly ssp { 142 entry: 143 ; ARM: t15 144 %add.ptr = getelementptr inbounds i8* %a, i64 -256 145 %0 = load i8* %add.ptr, align 2 146 ; ARM: mvn r{{[1-9]}}, #255 147 ; ARM: add r0, r0, r{{[1-9]}} 148 ; ARM: ldrsb r0, [r0] 149 ret i8 %0 150 } 151
