1 ; RUN: llc < %s -mtriple armv8 -mattr=+neon | FileCheck %s 2 3 define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind { 4 ; CHECK: vmaxnmq 5 ; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} 6 %tmp1 = load <4 x float>* %A 7 %tmp2 = load <4 x float>* %B 8 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) 9 ret <4 x float> %tmp3 10 } 11 12 define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind { 13 ; CHECK: vmaxnmd 14 ; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 15 %tmp1 = load <2 x float>* %A 16 %tmp2 = load <2 x float>* %B 17 %tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 18 ret <2 x float> %tmp3 19 } 20 21 define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind { 22 ; CHECK: vminnmq 23 ; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} 24 %tmp1 = load <4 x float>* %A 25 %tmp2 = load <4 x float>* %B 26 %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) 27 ret <4 x float> %tmp3 28 } 29 30 define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind { 31 ; CHECK: vminnmd 32 ; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 33 %tmp1 = load <2 x float>* %A 34 %tmp2 = load <2 x float>* %B 35 %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 36 ret <2 x float> %tmp3 37 } 38 39 declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone 40 declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone 41 declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone 42 declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone 43
