1 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s 2 3 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { 4 entry: 5 ; CHECK: daddu 6 %add = add nsw i64 %a1, %a0 7 ret i64 %add 8 } 9 10 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone { 11 entry: 12 ; CHECK: dsubu 13 %sub = sub nsw i64 %a0, %a1 14 ret i64 %sub 15 } 16 17 define i64 @f4(i64 %a0, i64 %a1) nounwind readnone { 18 entry: 19 ; CHECK: and 20 %and = and i64 %a1, %a0 21 ret i64 %and 22 } 23 24 define i64 @f5(i64 %a0, i64 %a1) nounwind readnone { 25 entry: 26 ; CHECK: or 27 %or = or i64 %a1, %a0 28 ret i64 %or 29 } 30 31 define i64 @f6(i64 %a0, i64 %a1) nounwind readnone { 32 entry: 33 ; CHECK: xor 34 %xor = xor i64 %a1, %a0 35 ret i64 %xor 36 } 37 38 define i64 @f7(i64 %a0) nounwind readnone { 39 entry: 40 ; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, 20 41 %add = add nsw i64 %a0, 20 42 ret i64 %add 43 } 44 45 define i64 @f8(i64 %a0) nounwind readnone { 46 entry: 47 ; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, -20 48 %sub = add nsw i64 %a0, -20 49 ret i64 %sub 50 } 51 52 define i64 @f9(i64 %a0) nounwind readnone { 53 entry: 54 ; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 20 55 %and = and i64 %a0, 20 56 ret i64 %and 57 } 58 59 define i64 @f10(i64 %a0) nounwind readnone { 60 entry: 61 ; CHECK: ori ${{[0-9]+}}, ${{[0-9]+}}, 20 62 %or = or i64 %a0, 20 63 ret i64 %or 64 } 65 66 define i64 @f11(i64 %a0) nounwind readnone { 67 entry: 68 ; CHECK: xori ${{[0-9]+}}, ${{[0-9]+}}, 20 69 %xor = xor i64 %a0, 20 70 ret i64 %xor 71 } 72 73 define i64 @f12(i64 %a, i64 %b) nounwind readnone { 74 entry: 75 ; CHECK: mult 76 %mul = mul nsw i64 %b, %a 77 ret i64 %mul 78 } 79 80 define i64 @f13(i64 %a, i64 %b) nounwind readnone { 81 entry: 82 ; CHECK: mult 83 %mul = mul i64 %b, %a 84 ret i64 %mul 85 } 86 87 define i64 @f14(i64 %a, i64 %b) nounwind readnone { 88 entry: 89 ; CHECK-LABEL: f14: 90 ; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]] 91 ; CHECK: teq $[[R0]], $zero, 7 92 ; CHECK: mflo 93 %div = sdiv i64 %a, %b 94 ret i64 %div 95 } 96 97 define i64 @f15(i64 %a, i64 %b) nounwind readnone { 98 entry: 99 ; CHECK-LABEL: f15: 100 ; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]] 101 ; CHECK: teq $[[R0]], $zero, 7 102 ; CHECK: mflo 103 %div = udiv i64 %a, %b 104 ret i64 %div 105 } 106 107 define i64 @f16(i64 %a, i64 %b) nounwind readnone { 108 entry: 109 ; CHECK-LABEL: f16: 110 ; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]] 111 ; CHECK: teq $[[R0]], $zero, 7 112 ; CHECK: mfhi 113 %rem = srem i64 %a, %b 114 ret i64 %rem 115 } 116 117 define i64 @f17(i64 %a, i64 %b) nounwind readnone { 118 entry: 119 ; CHECK-LABEL: f17: 120 ; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]] 121 ; CHECK: teq $[[R0]], $zero, 7 122 ; CHECK: mfhi 123 %rem = urem i64 %a, %b 124 ret i64 %rem 125 } 126 127 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 128 129 define i64 @f18(i64 %X) nounwind readnone { 130 entry: 131 ; CHECK: dclz $2, $4 132 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) 133 ret i64 %tmp1 134 } 135 136 define i64 @f19(i64 %X) nounwind readnone { 137 entry: 138 ; CHECK: dclo $2, $4 139 %neg = xor i64 %X, -1 140 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) 141 ret i64 %tmp1 142 } 143 144 define i64 @f20(i64 %a, i64 %b) nounwind readnone { 145 entry: 146 ; CHECK: nor 147 %or = or i64 %b, %a 148 %neg = xor i64 %or, -1 149 ret i64 %neg 150 } 151 152