1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s 2 3 ; CHECK: @fsub_f32 4 ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 5 6 define void @fsub_f32() { 7 %r0 = call float @llvm.R600.load.input(i32 0) 8 %r1 = call float @llvm.R600.load.input(i32 1) 9 %r2 = fsub float %r0, %r1 10 call void @llvm.AMDGPU.store.output(float %r2, i32 0) 11 ret void 12 } 13 14 declare float @llvm.R600.load.input(i32) readnone 15 16 declare void @llvm.AMDGPU.store.output(float, i32) 17 18 ; CHECK: @fsub_v2f32 19 ; CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z 20 ; CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y 21 define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { 22 entry: 23 %0 = fsub <2 x float> %a, %b 24 store <2 x float> %0, <2 x float> addrspace(1)* %out 25 ret void 26 } 27 28 ; CHECK: @fsub_v4f32 29 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 30 ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 31 ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 32 ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 33 define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { 34 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 35 %a = load <4 x float> addrspace(1) * %in 36 %b = load <4 x float> addrspace(1) * %b_ptr 37 %result = fsub <4 x float> %a, %b 38 store <4 x float> %result, <4 x float> addrspace(1)* %out 39 ret void 40 } 41
