1 // RUN: llvm-tblgen %s | FileCheck %s 2 3 class ValueType<int size, int value> { 4 int Size = size; 5 int Value = value; 6 } 7 8 def f32 : ValueType<32, 1>; // 2 x i64 vector value 9 10 class Intrinsic<string name> { 11 string Name = name; 12 } 13 14 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr, 15 list<dag> pattern> { 16 bits<8> Opcode = opcode; 17 dag OutOperands = oopnds; 18 dag InOperands = iopnds; 19 string AssemblyString = asmstr; 20 list<dag> Pattern = pattern; 21 } 22 23 def ops; 24 def outs; 25 def ins; 26 27 def set; 28 29 // Define registers 30 class Register<string n> { 31 string Name = n; 32 } 33 34 class RegisterClass<list<ValueType> regTypes, list<Register> regList> { 35 list<ValueType> RegTypes = regTypes; 36 list<Register> MemberList = regList; 37 } 38 39 def XMM0: Register<"xmm0">; 40 def XMM1: Register<"xmm1">; 41 def XMM2: Register<"xmm2">; 42 def XMM3: Register<"xmm3">; 43 def XMM4: Register<"xmm4">; 44 def XMM5: Register<"xmm5">; 45 def XMM6: Register<"xmm6">; 46 def XMM7: Register<"xmm7">; 47 def XMM8: Register<"xmm8">; 48 def XMM9: Register<"xmm9">; 49 def XMM10: Register<"xmm10">; 50 def XMM11: Register<"xmm11">; 51 def XMM12: Register<"xmm12">; 52 def XMM13: Register<"xmm13">; 53 def XMM14: Register<"xmm14">; 54 def XMM15: Register<"xmm15">; 55 56 def FR32 : RegisterClass<[f32], 57 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 58 XMM8, XMM9, XMM10, XMM11, 59 XMM12, XMM13, XMM14, XMM15]>; 60 61 class SDNode {} 62 def not : SDNode; 63 64 multiclass scalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> { 65 def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 66 !strconcat(asmstr, "\t$dst, $src"), 67 !if(!empty(patterns),[]<dag>,patterns[0])>; 68 def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 69 !strconcat(asmstr, "\t$dst, $src"), 70 !if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>; 71 } 72 73 multiclass vscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> { 74 def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 75 !strconcat(asmstr, "\t$dst, $src"), 76 !if(!empty(patterns),[]<dag>,patterns[0])>; 77 def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 78 !strconcat(asmstr, "\t$dst, $src"), 79 !if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>; 80 } 81 82 multiclass myscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> : 83 scalar<opcode, asmstr, patterns>, 84 vscalar<opcode, asmstr, patterns>; 85 86 defm NOT : myscalar<0x10, "not", [[], [(set FR32:$dst, (f32 (not FR32:$src)))]]>; 87 88 // CHECK: Pattern = [(set FR32:$dst, (f32 (not FR32:$src)))]; 89 // CHECK: Pattern = []; 90 // CHECK: Pattern = [(set FR32:$dst, (f32 (not FR32:$src)))]; 91 // CHECK: Pattern = []; 92
