1 # 2 # MIPS 5K 3 # 4 # As standard the CPU supports 2 performance counters. Event 0, 2, 3 and 4 5 # are available on both counters; the INSNS_EXECED is available on counter 0 6 # as event 0 and on counter 1 as event 1; the remaining are counter-specific. 7 # 8 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles 9 event:0x2 counters:0,1 um:zero minimum:500 name:LOADS_EXECED : Load/pref(x)/sync/cache-ops executed 10 event:0x3 counters:0,1 um:zero minimum:500 name:STORES_EXECED : Stores (including conditional stores) executed 11 event:0x4 counters:0,1 um:zero minimum:500 name:COND_STORES_EXECED : Conditional stores executed 12 13 # 14 # Events specific to counter 0 15 # 16 event:0x1 counters:0 um:zero minimum:500 name:INSN_FETCHED : Instructions fetched 17 event:0x5 counters:0 um:zero minimum:500 name:FAILED_COND_STORES : Failed conditional stores 18 event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_EXECED : Branches executed 19 event:0x7 counters:0 um:zero minimum:500 name:ITLB_MISSES : ITLB miss 20 event:0x8 counters:0 um:zero minimum:500 name:DTLB_MISSES : DTLB miss 21 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_MISS : Instruction cache miss 22 event:0xa counters:0 um:zero minimum:500 name:INSN_SCHEDULED : Instruction scheduled 23 event:0xe counters:0 um:zero minimum:500 name:DUAL_ISSUED_INSNS : Dual issued instructions executed 24 event:0xf counters:0 um:zero minimum:500 name:INSNS_EXECED : Instructions executed 25 26 # 27 # Events specific to counter 1 28 # 29 event:0x1 counters:1 um:zero minimum:500 name:INSNS_EXECED : Instructions executed 30 event:0x5 counters:1 um:zero minimum:500 name:FP_INSNS_EXECED : Floating-point instructions executed 31 event:0x6 counters:1 um:zero minimum:500 name:DCACHE_LINE_EVICTED : Data cache line evicted 32 event:0x7 counters:1 um:zero minimum:500 name:TLB_MISS_EXCEPTIONS : TLB miss exceptions 33 event:0x8 counters:1 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branch mispredicted 34 event:0x9 counters:1 um:zero minimum:500 name:DCACHE_MISS : Data cache miss 35 event:0xa counters:1 um:zero minimum:500 name:CONFLICT_STALL_M_STAGE : Instruction stall in M stage due to scheduling conflicts 36 event:0xf counters:1 um:zero minimum:500 name:COP2_INSNS_EXECED : COP2 instructions executed 37
